Relaxing non-volatility for fast and energy-efficient STT-RAM caches. - Clinton Wills Smullen IV; Vidyabhushan Mohan; Anurag Nigam; Sudhanva Gurumurthi; Mircea R. Stan (HPCA, 2011)

The STeTSiMS STT-RAM simulation and modeling system. - Clinton Wills Smullen IV; Anurag Nigam; Sudhanva Gurumurthi; Mircea R. Stan (ICCAD, 2011)

Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM). - Anurag Nigam; Clinton Wills Smullen IV; Vidyabhushan Mohan; Eugene Chen; Sudhanva Gurumurthi; Mircea R. Stan (ISLPED, 2011)

A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology. - Tz-Yi Liu; Tian Hong Yan; Roy Scheuerlein; Yingchang Chen; Jeffrey KoonYee Lee; Gopinath Balakrishnan; Gordon Yee; Henry Zhang; Alex Yap; Jingwen Ouyang; Takahiko Sasaki; Sravanti Addepalli; et al. (ISSCC, 2013)

A 130.7-mm2 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology. - Tz-Yi Liu; Tian Hong Yan; Roy Scheuerlein; Yingchang Chen; Jeffrey KoonYee Lee; Gopinath Balakrishnan; Gordon Yee; Henry Zhang; Alex Yap; Jingwen Ouyang; Takahiko Sasaki; Ali Al-Shamma; et al. (IEEE J. Solid State Circuits, 2014)

Varying Vector Representations and Integrating Meaning Shifts into a PageRank Model for Automatic Term Extraction. - Anurag Nigam; Anna Hätty; Sabine Schulte im Walde (LREC, 2020)