A Compact D-Band Phase Shifter with 0.1-degree Phase Resolution and 0.8-degree RMS Phase Error in 65 nm CMOS. - Takaya Uchino; Yudai Yamazaki; Sunghwan Park; Chenxin Liu; Anyi Tian; Abanob Shehata; Hiroyuki Sakai 009; Kazuaki Kunihiro; Atsushi Shirane; Kenichi Okada 001 (A-SSCC, 2024)

A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (VLSI Technology and Circuits, 2024)

A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (ASP-DAC, 2025)

A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (IEEE J. Solid State Circuits, 2025)