An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage. - Ye Lin; Yuandong Li; Heng Zhang 024; He Ma; Jingjing Lv; Anying Jiang; Yuan Du; Li Du (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An Offset-Cancellation Technique Using Charge-Trap Transistors and Asynchronous Programming Scheme. - Ye Lin; Anying Jiang; Jingjing Lv; Yuan Du; Li Du (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing. - Anying Jiang; Ye Lin; Jiayuan Chen; Wenhe Yin; Yize Wang; Mingqian Yang; Li Du; Yuan Du (ISCAS, 2025)