Anzhela Yu. Matrosova
Orcid: 0000-0002-8662-4740Affiliations:
- Tomsk State University, Tomsk, Russia
According to our database1,
Anzhela Yu. Matrosova
authored at least 51 papers
between 2000 and 2022.
Collaborative distances:
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Bibliography
2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits.
Autom. Remote. Control., 2021
Proceedings of the IEEE East-West Design & Test Symposium, 2021
Proceedings of the IEEE East-West Design & Test Symposium, 2021
2020
Masking Internal Node Logical Faults and Trojan Circuits Injections with Using SAT Solvers.
Proceedings of the IEEE International Conference on Automation, 2020
2019
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
2018
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design.
J. Electron. Test., 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018
Proceedings of the IEEE International Conference on Automation, 2018
2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Test pattern generation to detect multiple faults in ROBDD based combinational circuits.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the IEEE International Conference on Automation, 2016
2015
Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits.
Autom. Remote. Control., 2015
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015
Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015
Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Proceedings of the 2014 East-West Design & Test Symposium, 2014
Combinational part structure simplification of fully delay testable sequential circuit.
Proceedings of the 2014 East-West Design & Test Symposium, 2014
Proceedings of the 2014 East-West Design & Test Symposium, 2014
2013
Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs.
Autom. Remote. Control., 2013
Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques.
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the East-West Design & Test Symposium, 2013
Proceedings of the East-West Design & Test Symposium, 2013
2011
Proceedings of the 9th East-West Design & Test Symposium, 2011
2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
2007
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
2001
Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000