Self-Checking FSM Design with Observing only FSM Outputs. - Anzhela Yu. Matrosova; Sergey Ostanin (IOLTW, 2000)

Self-checking Synchronous FSM Network Design with Low Overhead. - Anzhela Yu. Matrosova; Ilya Levin; Sergey Ostanin (VLSI Design, 2000)

Survivable Self-Checking Sequential Circuits. - Anzhela Yu. Matrosova; Sergey Ostanin; Ilya Levin (DFT, 2001)

Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation. - Anzhela Yu. Matrosova; K. Nikitin; Olga Goloubeva (IOLTW, 2001)

Survivable Discrete Circuits Design. - Anzhela Yu. Matrosova; Valentina Andreeva; Yu. Sedov (IOLTW, 2002)

Designing FPGA based Self-Testing Checkers for m-out-of-n Codes. - Anzhela Yu. Matrosova; Vladimir Ostrovsky; Ilya Levin; K. Nikitin (IOLTS, 2003)

Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs. - Anjela Yu. Matrosova; Ekaterina Loukovnikova; Sergei Ostanin; Alexandra Zinchuk; Ekaterina Nikolaeva (DFT, 2007)

Path delay faults and ENF. - Anzhela Yu. Matrosova; Valeriy B. Lipsky; Alexey Melnikov 002; Virendra Singh (EWDTS, 2010)

PDFs testing of combinational circuits based on covering ROBDDs. - Anjela Yu. Matrosova; Ekaterina Nikolaeva (EWDTS, 2010)

Fault grading using Instruction-Execution graph. - K. R. Vinutha; Virendra Singh; Anzhela Yu. Matrosova; Manoj Singh Gaur (EWDTS, 2010)

Selection of the state variables for partial enhanced scan techniques. - Anzhela Yu. Matrosova; Alexey Melnikov 002; Ruslan Mukhamedov; Virendra Singh (EWDTS, 2011)

Delay testable sequential circuit designs. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Virendra Singh (EWDTS, 2013)

PDF testability of the circuits derived by special covering ROBDDs with gates. - Anzhela Yu. Matrosova; Ekaterina Nikolaeva; Dmitry Kudin; Virendra Singh (EWDTS, 2013)

Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. - Anzhela Yu. Matrosova; Sergey Ostanin; Alexey Melnikov 002; Virendra Singh (EWDTS, 2013)

Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. - Anzhela Yu. Matrosova; Sergey A. Ostanin; Virendra Singh (Autom. Remote. Control., 2013)

Combinational circuits without false paths. - Anzhela Yu. Matrosova; Dmitry Kudin; Ekaterina Nikolaeva (EWDTS, 2014)

Combinational part structure simplification of fully delay testable sequential circuit. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Elena Roumjantseva (EWDTS, 2014)

Partially programmable circuit design. - Anzhela Yu. Matrosova; Sergey Ostanin; Irina Kirienko; Virendra Singh (EWDTS, 2014)

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. - Satyadev Ahlawat; Jaynarayan T. Tudu; Anzhela Yu. Matrosova; Virendra Singh (ATS, 2015)

Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit. - Anzhela Yu. Matrosova; Sergey Ostanin; Irina Kirienko (DDECS, 2015)

Fully delay and multiple stuck-at faults testable FSM design. - Anzhela Yu. Matrosova; Valentina Andreeva; V. Tomkov (EWDTS, 2015)

Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Toral Shah (EWDTS, 2015)

Fault-tolerant high performance scheme design. - Anzhela Yu. Matrosova; Sergey Ostanin; Irina Kirienko; Ekaterina Nikolaeva (EWDTS, 2015)

Simplification of fully delay testable combinational circuits. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Toral Shah (IOLTS, 2015)

PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. - Toral Shah; Anzhela Yu. Matrosova; Virendra Singh (VDAT, 2015)

Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits. - Anzhela Yu. Matrosova; Valeriy B. Lipskii (Autom. Remote. Control., 2015)

Patching circuit design based on reserved CLBs. - Anjela Yu. Matrosova; Sergey Ostanin; Valentina Andreeva (AQTR, 2016)

ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself. - Anzhela Yu. Matrosova; Valentina Andreeva; Alexey Melnikov 002 (EWDTS, 2016)

Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov (EWDTS, 2016)

A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit. - Sergey Ostanin; Anzhela Yu. Matrosova; Natalia Butorina; V. Lavrov (EWDTS, 2016)

ROBDD based path delay fault testable combinational circuit synthesis. - Toral Shah; Virendra Singh; Anzhela Yu. Matrosova (EWDTS, 2016)

A high performance scan flip-flop design for serial and mixed mode scan test. - Satyadev Ahlawat; Jaynarayan T. Tudu; Anzhela Yu. Matrosova; Virendra Singh (IOLTS, 2016)

A fault-tolerant sequential circuit design for SAFs and PDFs soft errors. - Anzhela Yu. Matrosova; Sergey Ostanin; Irina Kirienko; Ekaterina Nikolaeva (IOLTS, 2016)

Preventing and masking Trojan circuits triggering out of working area. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Sergei Ostanin; Irina Kirienko (ECCTD, 2017)

Detection and masking of Trojan Circuits in sequential logic. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Sergey Ostanin; Ekaterina Nikolaeva (EWDTS, 2017)

Logic circuit design with gates, LUTs and MUXs oriented to mask faults. - Anzhela Yu. Matrosova; Sergey Ostanin; D. Tretyakov; Natalia Butorina (EWDTS, 2017)

Trojan circuits preventing and masking in sequential circuits. - Anjela Yu. Matrosova; Eugeniy Mitrofanov; Sergei Ostanin; Irina Kirienko (IOLTS, 2017)

Test pattern generation to detect multiple faults in ROBDD based combinational circuits. - Toral Shah; Anzhela Yu. Matrosova; Virendra Singh (IOLTS, 2017)

Testing multiple stuck-at faults of ROBDD based combinational circuit design. - Toral Shah; Anzhela Yu. Matrosova; Binod Kumar 001; Masahiro Fujita; Virendra Singh (LATS, 2017)

Trojan circuits masking and debugging of combinational circuits with LUT insertion. - Anzhela Yu. Matrosova; Sergey Ostanin (AQTR, 2018)

Forming Patch Functions and Combinational Circuit Rectification. - Anjela Yu. Matrosova; Semen Chernyshov; Gennadiy Goshin; Dmitry Kudin (EWDTS, 2018)

Finding False Paths for Sequential Circuits Using Operations on ROBDDs. - Anzhela Yu. Matrosova; Sergei Ostanin; Semen Chernyshov (IOLTS, 2018)

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. - Toral Shah; Anzhela Yu. Matrosova; Masahiro Fujita; Virendra Singh (J. Electron. Test., 2018)

Deriving Low Power Test Sequences Detecting Robust Testable PDFs. - Anjela Yu. Matrosova; Valentina Andreeva; V. Tychinskiy (EWDTS, 2019)

Masking Robust Testable PDFs. - Anzhela Yu. Matrosova; Sergei Ostanin; Semen Chernyshov (EWDTS, 2019)

Masking Internal Node Faults and Trojan Circuits in Logical Circuits. - Anzhela Yu. Matrosova; V. Provkin; Ekaterina Nikolaeva (EWDTS, 2019)

Masking Internal Node Logical Faults and Trojan Circuits Injections with Using SAT Solvers. - Anzhela Yu. Matrosova; V. Provkin (AQTR, 2020)

SAT Solvers Application of Deriving All Test Pairs Detecting Robust Testable PDFs. - Anjela Yu. Matrosova; Valentina Andreeva; V. Tychinskiy (EWDTS, 2021)

Applying Incompletely Specified Boolean Functions for Patch Circuit Generation. - Anzhela Yu. Matrosova; V. Provkin (EWDTS, 2021)

Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits. - Anzhela Yu. Matrosova; Semen Chernyshov; O. Kh. Kim; Ekaterina Nikolaeva (Autom. Remote. Control., 2021)

Deriving FSM-based tests using $a, b- text{faults}$ for Logic Circuits. - Andrey Laputenko; Nina Yevtushenko 001; Valentina Andreeva; Anzhela Yu. Matrosova (ISVLSI, 2022)