Reducing Exit Stub Memory Consumption in Code Caches. - Apala Guha; Kim M. Hazelwood; Mary Lou Soffa (HiPEAC, 2007)

Virtual Execution Environments: Support and Tools. - Apala Guha; Jason Hiser; Naveen Kumar 002; Jing Yang 003; Min Zhao 009; Shukang Zhou; Bruce R. Childers; Jack W. Davidson; Kim M. Hazelwood; Mary Lou Soffa (IPDPS, 2007)

Balancing memory and performance through selective flushing of software code caches. - Apala Guha; Kim M. Hazelwood; Mary Lou Soffa (CASES, 2010)

DBT path selection for holistic memory efficiency and performance. - Apala Guha; Kim M. Hazelwood; Mary Lou Soffa (VEE, 2010)

Abstract: An Exascale Workload Study. - Prasanna Balaprakash; Darius Buntinas; Anthony Chan; Apala Guha; Rinku Gupta; Sri Hari Krishna Narayanan; Andrew A. Chien; Paul D. Hovland; Boyana Norris (SC Companion, 2012)

Poster: An Exascale Workload Study. - Prasanna Balaprakash; Darius Buntinas; Anthony Chan; Apala Guha; Rinku Gupta; Sri Hari Krishna Narayanan; Andrew A. Chien; Paul D. Hovland; Boyana Norris (SC Companion, 2012)

Memory optimization of dynamic binary translators for embedded systems. - Apala Guha; Kim M. Hazelwood; Mary Lou Soffa (ACM Trans. Archit. Code Optim., 2012)

Exascale workload characterization and architecture implications. - Prasanna Balaprakash; Darius Buntinas; Anthony Chan; Apala Guha; Rinku Gupta; Sri Hari Krishna Narayanan; Andrew A. Chien; Paul D. Hovland; Boyana Norris (ISPASS, 2013)

Systematic evaluation of workload clustering for extremely energy-efficient architectures. - Apala Guha; Yao Zhang; Raihan Ur Rasool; Andrew A. Chien (SIGARCH Comput. Archit. News, 2013)

On the applicability of simple cache models for modern processors. - Rakhi Hemani; Subhasis Banerjee; Apala Guha (ICGHPC, 2016)

Easy and expressive LLC contention model. - Rakhi Hemani; Subhasis Banerjee; Apala Guha (HPCS, 2016)

Chainsaw: Von-neumann accelerators to leverage fused instruction chains. - Amirali Sharifian; Snehasish Kumar; Apala Guha; Arrvindh Shriraman (MICRO, 2016)

The Impact of Toxic Language on the Health of Reddit Communities. - Shruthi Mohan; Apala Guha; Michael Harris; Fred Popowich; Ashley Schuster; Chris Priebe (Canadian AI, 2017)

The interaction of last-level-cache mechanisms on modern processors. - Rakhi Hemani; Subhasis Banerjee; Apala Guha (MEMSYS, 2017)

DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable Architectures. - Manideepa Mukherjee; Alexander Fell; Apala Guha (VLSID, 2017)

TAPAS: Generating Parallel Accelerators from Parallel Programs. - Steve Margerm; Amirali Sharifian; Apala Guha; Arrvindh Shriraman; Gilles Pokam (MICRO, 2018)

Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators. - Apala Guha; Naveen Vedula; Arrvindh Shriraman (PACT, 2019)

μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. - Amirali Sharifian; Reza Hojabr; Navid Rahimi; Sihao Liu; Apala Guha; Tony Nowatzki; Arrvindh Shriraman (MICRO, 2019)