Reverse Engineering Word-Level Models from Look-Up Table Netlists. - Ram Venkat Narayanan; Aparajithan Nathamuni Venkatesan; Kishore Pula; Sundarakumar Muthukumaran; Ranga Vemuri (ISQED, 2023)

Reverse Engineering of RTL Controllers from Look-Up Table Netlists. - Sundarakumar Muthukumaran; Aparajithan Nathamuni Venkatesan; Kishore Pula; Ram Venkat Narayanan; Ranga Vemuri; John Marty Emmert (ISVLSI, 2023)

RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks. - Kishore Pula; Aparajithan Nathamuni Venkatesan; Ram Venkat Narayanan; Sundarakumar Muthukumaran; Ranga Vemuri; John Marty Emmert (MWSCAS, 2023)

Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. - Aparajithan Nathamuni Venkatesan; Ram Venkat Narayanan; Kishore Pula; Sundarakumar Muthukumaran; Ranga Vemuri (VLSID, 2023)