Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. - Kwen-Siong Chong; Aparna Shreedhar; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Chao Wang 096; Jun Zhou 017; Bah-Hwee Gwee; Joseph S. Chang (AsianHOST, 2019)

Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. - Aparna Shreedhar; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; L. Nalangilli; Wei Shu; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2019)