Location of the Largest Empty Rectangle among Arbitrary Obstacles. - Subhas C. Nandy; Arani Sinha; Bhargab B. Bhattacharya (FSTTCS, 1994)

Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction. - Arani Sinha; Salim Chowdhury (CICC, 1999)

Validation and test generation for oscillatory noise in VLSI interconnects. - Arani Sinha; Sandeep K. Gupta 001; Melvin A. Breuer (ICCAD, 1999)

An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. - Arani Sinha; Sandeep K. Gupta 001; Melvin A. Breuer (Asian Test Symposium, 2003)

Simulating the Effects of Process Variations on Capacitive Crosstalk. - Arani Sinha; Shahin Nazarian; T. M. Mak (ICECS, 2006)

On-Chip Inductance in X Architecture Enabled Design. - Santosh Shah; Arani Sinha; Li Song; Narain D. Arora (ISQED, 2007)

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults. - Arani Sinha; Sandeep K. Gupta 001; Melvin A. Breuer (ATS, 2008)

Panel: Analog Characterization and Test: The Long Road to Realization. - Arani Sinha; Amitava Majumdar 002; Vasu Ganti (VTS, 2009)

Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality? - Arani Sinha (VTS, 2010)

A Novel mechanism for speed characterization during delay test. - Amitava Majumdar 002; Arani Sinha; Nehal Patel; Ramamurthy Setty; Yan Dong; Shu-Hsuan Chou (VTS, 2011)

The buck stops with wafer test: Dream or reality? - Suriyaprakash Natarajan; Arani Sinha (VTS, 2011)

The bang for the buck with resiliency: Yield or field? - Arani Sinha; Suriyaprakash Natarajan (VTS, 2011)

Path selection based on static timing analysis considering input necessary assignments. - Bo Yao 002; Arani Sinha; Irith Pomeranz (VTS, 2013)

DFM-aware fault model and ATPG for intra-cell and inter-cell defects. - Arani Sinha; Sujay Pandey; Ayush Singhal; Alodeep Sanyal; Alan Schmaltz (ITC, 2017)

Innovative practices session 1C screening for layout sensitive defects. - Arani Sinha; Nitin Chaudhary (VTS, 2017)

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. - Naixing Wang; Irith Pomeranz; Sudhakar M. Reddy; Arani Sinha; Srikanth Venkataraman (DATE, 2019)

Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology. - Sujay Pandey; Sanya Gupta; Madhu Sudhan L.; Suriya Natarajan; Arani Sinha; Abhijit Chatterjee (ITC, 2019)

Analog/Mixed Signal IP DFx from a Foundry perspective. - Salem Abdennadher; Arani Sinha; Yonghyun Kim (LATS, 2019)

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. - Naixing Wang; Irith Pomeranz; Sudhakar M. Reddy; Arani Sinha; Srikanth Venkataraman (ACM Trans. Design Autom. Electr. Syst., 2019)

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. - Sujay Pandey; Zhiwei Liao; Shreyas Nandi; Sanya Gupta; Suriyaprakash Natarajan; Arani Sinha; Adit D. Singh; Abhijit Chatterjee (ITC, 2020)

Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests. - Ankit Shah; Raman Nayyar; Arani Sinha (IEEE Des. Test, 2020)

Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction. - Sandip Ray; Arani Sinha (ETS, 2021)

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. - Sujay Pandey; Zhiwei Liao; Shreyas Nandi; Suriyaprakash Natarajan; Arani Sinha; Adit D. Singh; Abhijit Chatterjee (VTS, 2021)

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. - Hari Addepalli; Irith Pomeranz; M. Enamul Amyeen; Suriyaprakash Natarajan; Arani Sinha; Srikanth Venkataraman (ATS, 2022)

Multi-die Parallel Test Fabric for Scalability and Pattern Reusability. - Arani Sinha; Yonsang Cho; Jon Easter; Meizel V. Leiva Rojas (ITC, 2022)

Innovative Practices Track: Silent Data Errors. - Arani Sinha (VTS, 2022)

Innovative Practices Track: Next Generation Test Standards. - Arani Sinha (VTS, 2022)

Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure. - Arani Sinha; Glenn Colón-Bonet; Michael Fahy; Pankaj Pant; Haijing Mao; Akhilesh Shukla (ITC, 2023)

Generating Storage-Aware Test Sets Targeting Several Fault Models. - Hari Addepalli; Irith Pomeranz; M. Enamul Amyeen; Suriyaprakash Natarajan; Arani Sinha; Srikanth Venkataraman (ISVLSI, 2024)

Functional State Extraction using Scan DFT. - Ilya Wagner; Pankaj Pant; Arani Sinha (ITC, 2024)

Innovative Practices Track: Session 3 Test and Functional Safety Standards. - Arani Sinha (VTS, 2024)

Innovative Practices Track: Session 4 AI Applications in Test. - Arani Sinha; Stefano Di Carlo (VTS, 2024)

Innovative Practices Track: Session 2 Silent Data Corruption. - Arani Sinha; Adit D. Singh (VTS, 2024)

Special Session: Trustworthy Hardware-AI at the Cloud. - Francesco Angione; Paolo Bernardi; Alberto Bosio; Harish Dattatraya Dixit; Salvatore Pappalardo; Annachiara Ruospo; Ernesto Sánchez 001; Arani Sinha; Vittorio Turco (VTS, 2025)