On Efficient Normal Basis Multiplication. - Arash Reyhani-Masoleh; M. Anwarul Hasan (INDOCRYPT, 2000)

Error Detection in Polynomial Basis Multipliers over Binary Extension Fields. - Arash Reyhani-Masoleh; M. Anwarul Hasan (CHES, 2002)

Efficient digit-serial normal basis multipliers over GF(2m). - Arash Reyhani-Masoleh; M. Anwar Hasan (ISCAS (5), 2002)

A New Construction of Massey-Omura Parallel Multiplier over GF(2m). - Arash Reyhani-Masoleh; M. Anwarul Hasan (IEEE Trans. Computers, 2002)

Low Complexity Sequential Normal Basis Multipliers over GF(2m). - Arash Reyhani-Masoleh; M. Anwarul Hasan (IEEE Symposium on Computer Arithmetic, 2003)

On Low Complexity Bit Parallel Polynomial Basis Multipliers. - Arash Reyhani-Masoleh; M. Anwarul Hasan (CHES, 2003)

Efficient Multiplication Beyond Optimal Normal Bases. - Arash Reyhani-Masoleh; M. Anwarul Hasan (IEEE Trans. Computers, 2003)

Fast Normal Basis Multiplication Using General Purpose Processors. - Arash Reyhani-Masoleh; M. Anwarul Hasan (IEEE Trans. Computers, 2003)

Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m}). - Arash Reyhani-Masoleh; M. Anwar Hasan (IEEE Trans. Computers, 2004)

Efficient digit-serial normal basis multipliers over binary extension fields. - Arash Reyhani-Masoleh; M. Anwar Hasan (ACM Trans. Embed. Comput. Syst., 2004)

Towards fault-tolerant cryptographic computations over finite fields. - Arash Reyhani-Masoleh; M. Anwar Hasan (ACM Trans. Embed. Comput. Syst., 2004)

Low Complexity Word-Level Sequential Normal Basis Multipliers. - Arash Reyhani-Masoleh; M. Anwar Hasan (IEEE Trans. Computers, 2005)

Parity Prediction of S-Box for AES. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (CCECE, 2006)

Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (DFT, 2006)

Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases. - Arash Reyhani-Masoleh (IEEE Trans. Computers, 2006)

Fault Detection Architectures for Field Multiplication Using Polynomial Bases. - Arash Reyhani-Masoleh; M. Anwar Hasan (IEEE Trans. Computers, 2006)

Fault Detection Structures for the Montgomery Multiplication over Binary Extension Fields. - Arash Hariri; Arash Reyhani-Masoleh (FDTC, 2007)

A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (FDTC, 2007)

High-speed parallel CRC circuits. - Christopher Kennedy; Arash Reyhani-Masoleh (ACSCC, 2008)

A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (CHES, 2008)

A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases. - Arash Reyhani-Masoleh (CHES, 2008)

A Key Management Scheme for Cluster Based Wireless Sensor Networks. - Reza Azarderakhsh; Arash Reyhani-Masoleh; Zine-Eddine Abid (EUC (2), 2008)

Key Management for Wireless Sensor Networks Using Trusted Neighbors. - Yuan Xue; Helmut Jürgensen; Reza Azarderakhsh; Arash Reyhani-Masoleh (EUC (2), 2008)

Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields. - Arash Hariri; Arash Reyhani-Masoleh (WAIFI, 2008)

High-speed CRC computations using improved state-space transformations. - Christopher Kennedy; Arash Reyhani-Masoleh (EIT, 2009)

A low-cost S-box for the Advanced Encryption Standard using normal basis. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (EIT, 2009)

Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (J. Electron. Test., 2009)

Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m). - Arash Hariri; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2009)

A Modified Low Complexity Digit-Level Gaussian Normal Basis Multiplier. - Reza Azarderakhsh; Arash Reyhani-Masoleh (WAIFI, 2010)

Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2010)

Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (DFT, 2011)

A High-Performance Fault Diagnosis Approach for the AES SubBytes Utilizing Mixed Bases. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (FDTC, 2011)

Secure Clustering and Symmetric Key Establishment in Heterogeneous Wireless Sensor Networks. - Reza Azarderakhsh; Arash Reyhani-Masoleh (EURASIP J. Wirel. Commun. Netw., 2011)

A Fault Detection Scheme for the FPGA Implementation of SHA-1 and SHA-512 Round Computations. - Mohsen Bahramali; Jin Jiang 001; Arash Reyhani-Masoleh (J. Electron. Test., 2011)

Concurrent Error Detection in Montgomery Multiplication over Binary Extension Fields. - Arash Hariri; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2011)

A Low-Power High-Performance Concurrent Fault Detection Approach for the Composite Field S-Box and Inverse S-Box. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2011)

Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension Fields. - Arash Hariri; Arash Reyhani-Masoleh (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM. - Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2012)

Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis. - Reza Azarderakhsh; Arash Reyhani-Masoleh (IEEE Trans. Very Large Scale Integr. Syst., 2012)

On Countermeasures Against Fault Attacks on Elliptic Curve Cryptography Using Fault Detection. - Arash Hariri; Arash Reyhani-Masoleh (Fault Analysis in Cryptography, 2012)

Low-Complexity Multiplier Architectures for Single and Hybrid-Double Multiplications in Gaussian Normal Bases. - Reza Azarderakhsh; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2013)

High-Performance Implementation of Point Multiplication on Koblitz Curves. - Reza Azarderakhsh; Arash Reyhani-Masoleh (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm. - Siavash Bayat Sarmadi; Mehran Mozaffari Kermani; Arash Reyhani-Masoleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

New Implementations of the WG Stream Cipher. - Hayssam El-Razouk; Arash Reyhani-Masoleh; Guang Gong (IEEE Trans. Very Large Scale Integr. Syst., 2014)

New Bit-Level Serial GF (2m) Multiplication Using Polynomial Basis. - Hayssam El-Razouk; Arash Reyhani-Masoleh (ARITH, 2015)

New Regular Radix-8 Scheme for Elliptic Curve Scalar Multiplication without Pre-Computation. - Ebrahim A. Hasan Abdulrahman; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2015)

New Hardware Implementations of WG(29, 11) and WG-16 Stream Ciphers Using Polynomial Basis. - Hayssam El-Razouk; Arash Reyhani-Masoleh; Guang Gong (IEEE Trans. Computers, 2015)

Comments on "Low-Latency Digit-Serial Systolic Double Basis Multiplier over GF(2m) Using Subquadratic Toeplitz Matrix-Vector Product Approach". - Arash Reyhani-Masoleh (IEEE Trans. Computers, 2015)

Parallel and High-Speed Computations of Elliptic Curve Cryptography Using Hybrid-Double Multipliers. - Reza Azarderakhsh; Arash Reyhani-Masoleh (IEEE Trans. Parallel Distributed Syst., 2015)

A CRC-Based Concurrent Fault Detection Architecture for Galois/Counter Mode (GCM). - Amir Ali Kouzeh Geran; Arash Reyhani-Masoleh (ARITH, 2016)

Keymill: Side-Channel Resilient Key Generator, A New Concept for SCA-Security by Design - A New Concept for SCA-Security by Design. - Mostafa M. I. Taha; Arash Reyhani-Masoleh; Patrick Schaumont (SAC, 2016)

Keymill: Side-Channel Resilient Key Generator. - Mostafa M. I. Taha; Arash Reyhani-Masoleh; Patrick Schaumont (IACR Cryptol. ePrint Arch., 2016)

High-Speed Hybrid-Double Multiplication Architectures Using New Serial-Out Bit-Level Mastrovito Multipliers. - Ebrahim A. Hasan Abdulrahman; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2016)

New Architectures for Digit-Level Single, Hybrid-Double, Hybrid-Triple Field Multiplications and Exponentiation Using Gaussian Normal Bases. - Hayssam El-Razouk; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2016)

Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation. - Dipanwita Gangopadhyay; Arash Reyhani-Masoleh (IEEE Trans. Computers, 2016)

A New Multiplicative Inverse Architecture in Normal Basis Using Novel Concurrent Serial Squaring and Multiplication. - Amin Monfared; Hayssam El-Razouk; Arash Reyhani-Masoleh (ARITH, 2017)

Stateless leakage resiliency from NLFSRs. - Mostafa M. I. Taha; Arash Reyhani-Masoleh; Patrick Schaumont (HOST, 2017)

New Area Record for the AES Combined S-Box/Inverse S-Box. - Arash Reyhani-Masoleh; Mostafa M. I. Taha; Doaa Ashmawy (ARITH, 2018)

Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines. - Amir Ardakani; Shahriar B. Shokouhi; Arash Reyhani-Masoleh (Integr., 2018)

Smashing the Implementation Records of AES S-box. - Arash Reyhani-Masoleh; Mostafa M. I. Taha; Doaa Ashmawy (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018)

New Multiplicative Inverse Architectures Using Gaussian Normal Basis. - Arash Reyhani-Masoleh; Hayssam El-Razouk; Amin Monfared (IEEE Trans. Computers, 2019)

New Low-Area Designs for the AES Forward, Inverse and Combined S-Boxes. - Arash Reyhani-Masoleh; Mostafa M. I. Taha; Doaa Ashmawy (IEEE Trans. Computers, 2020)

A Faster Hardware Implementation of the AES S-box. - Doaa Ashmawy; Arash Reyhani-Masoleh (ARITH, 2021)

Secure and Efficient Exponentiation Architectures Using Gaussian Normal Basis. - Amin Monfared; Mostafa M. I. Taha; Arash Reyhani-Masoleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A New 16-Bit IoT ASIC Design for the AES Encryption Algorithm. - Doaa Ashmawy; Arash Reyhani-Masoleh (ISCAS, 2025)