Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. - Arash Saifhashemi; Hossein Pedram (DAC, 2003)

MILO: personal robot platform. - Behnam Salemi; Jorge Reis; Arash Saifhashemi; Fred Nikgohar (IROS, 2005)

High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog. - Arash Saifhashemi; Peter A. Beerel (CPA, 2005)

Notes On Pulse Signaling. - Jo C. Ebergen; Steve Furber; Arash Saifhashemi (ASYNC, 2007)

SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces. - Arash Saifhashemi; Peter A. Beerel (CPA, 2011)

Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines. - Arash Saifhashemi; Peter A. Beerel (PATMOS, 2012)

Reconditioning: Automatic Power Optimization of QDI Circuits. - Arash Saifhashemi; Hsin-Ho Huang; Peter A. Beerel (ASYNC, 2014)

Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis. - Arash Saifhashemi; Dylan Hand; Peter A. Beerel; William Koven; Hong Wang (ASYNC, 2014)

Logical equivalence checking of asynchronous circuits using commercial tools. - Arash Saifhashemi; Hsin-Ho Huang; Priyanka Bhalerao; Peter A. Beerel (DATE, 2015)

Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits. - Arash Saifhashemi; Hsin-Ho Huang; Peter A. Beerel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)