A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth. - Arashk Norouzpour-Shirazi; S. Arash Mirhaj; Shahin Jafarabadi-Ashtiani; Omid Shoaei (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Linearity improvement of open-loop NMOS source-follower sample and hold circuits. - Arashk Norouzpour-Shirazi; S. Arash Mirhaj; Shahin Jafarabadi-Ashtiani; Omid Shoaei (IET Circuits Devices Syst., 2011)

High speed sample and hold design using closed-loop pole-zero cancelation. - S. Arash Mirhaj; Arashk Norouzpour-Shirazi; Shahin Jafarabadi-Ashtiani; Omid Shoaei (Microelectron. J., 2011)

An FPGA-Based Interface System for High-Frequency Bulk-Acoustic-Wave Microgyroscopes With In-Run Automatic Mode-Matching. - Chong Li 006; Haoran Wen; Samuel Wisher; Arashk Norouzpour-Shirazi; Jun-Yang Lei; Hua Chen; Farrokh Ayazi (IEEE Trans. Instrum. Meas., 2020)