A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. - Arasu T. Senthil; C. P. Ravikumar; Soumitra Kumar Nandy (ITC, 2005)

An Overlap Removal Algorithm for Macrocell Placement in VLSI Layouts. - M. Thenappan; Arasu T. Senthil; K. M. Sreekanth; Ramesh S. Guzar (ICCTA, 2007)

Low-Power Hierarchical Scan Test for Multiple Clock Domains. - Arasu T. Senthil; C. P. Ravikumar; S. K. Nandy 001 (J. Low Power Electron., 2007)