Lifting kernel-based sprite codec. - Aravind Dasu; Sethuraman Panchanathan (VCIP, 2001)

Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing. - Ali Akoglu; Aravind Dasu; Arvind Sudarsanam; Mayur Srinivasan; Sethuraman Panchanathan (IPDPS, 2002)

Reconfigurable media processing. - Aravind Dasu; Sethuraman Panchanathan (Parallel Comput., 2002)

A survey of media processing approaches. - Aravind Dasu; Sethuraman Panchanathan (IEEE Trans. Circuits Syst. Video Technol., 2002)

An Analysis Tool Set for Reconfigurable Media Processing. - Aravind Dasu; Ali Akoglu; Sethuraman Panchanathan (Engineering of Reconfigurable Systems and Algorithms, 2003)

Cluster Extraction for Hybrid FPGA Architecture in Computation Intensive Applications. - Ali Akoglu; Aravind Dasu; Sethuraman Panchanathan (ERSA, 2004)

Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures. - Arvind Sudarsanam; Aravind Dasu; Sethuraman Panchanathan (ERSA, 2004)

A wavelet-based sprite codec. - Aravind Dasu; Sethuraman Panchanathan (IEEE Trans. Circuits Syst. Video Technol., 2004)

A Fast and Efficient FPGA-Based Implementation for Solving a System of Linear Interval Equations. - Arvind Sudarsanam; Aravind Dasu (FPT, 2005)

High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications. - Aravind Dasu; Arvind Sudarsanam (IPDPS, 2005)

Memory support design for LU decomposition on the starbridge hyper-computer. - Seth Young; Arvind Sudarsanam; Aravind Dasu; Thomas Hauser (FPT, 2006)

A Reconfigurable Load Balancing Architecture for Molecular Dynamics. - Jonathan Phillips; Matthew Areno; Chris Rogers; Aravind Dasu; Brandon Eames (IPDPS, 2007)

Performance of a LU decomposition on a multi-FPGA system compared to a low power commodity microprocessor system. - Thomas Hauser; Aravind Dasu; Arvind Sudarsanam; Seth Young (Scalable Comput. Pract. Exp., 2007)

Hardware/Software Co-designed Extended Kalman Filter on an FPGA. - Robert Collier Barnes; Aravind Dasu (ERSA, 2008)

PRR-PRR Dynamic Relocation. - Arvind Sudarsanam; Ramachandra Kallam; Aravind Dasu (IEEE Comput. Archit. Lett., 2009)

Methodology to derive context adaptable architectures for FPGAs. - Jonathan Phillips; Arvind Sudarsanam; Harikrishna Samala; Ramachandra Kallam; J. Carver; Aravind Dasu (IET Comput. Digit. Tech., 2009)

Analysis and Design of a Context Adaptable SAD/MSE Architecture. - Arvind Sudarsanam; Aravind Dasu; Karthik Vaithianathan (Int. J. Reconfigurable Comput., 2009)

Welcome message. - Jürgen Becker 001; Eli Bozorgzadeh; João M. P. Cardoso; Aravind Dasu (IPDPS Workshops, 2010)

Memory architecture template for Fast Block Matching algorithms on FPGAs. - Shant Chandrakar; Abraham Clements; Arvind Sudarsanam; Aravind Dasu (IPDPS Workshops, 2010)

Self-configurable architecture for reusable systems with Accelerated Relocation Circuit (SCARS-ARC). - Adarsha Sreeramareddy; Ramachandra Kallam; Aravind Dasu; Ali Akoglu (IPDPS Workshops, 2010)

Methodology to derive resource aware context adaptable architectures for FPGAs. - Harikrishna Samala; Aravind Dasu (IET Comput. Digit. Tech., 2010)

Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms. - Arvind Sudarsanam; Robert Collier Barnes; J. Carver; Ramachandra Kallam; Aravind Dasu (IET Comput. Digit. Tech., 2010)

Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010). - Aravind Dasu; João M. P. Cardoso; Eli Bozorgzadeh; Jürgen Becker 001 (Int. J. Reconfigurable Comput., 2011)

A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM. - Peter Gadfort; Aravind Dasu; Ali Akoglu; Yoon Kah Leow; Michael Fritze (SoCC, 2014)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Sergey Y. Shumarayev; Aravind Dasu (FPGA, 2018)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Aravind Dasu; Sergey Y. Shumarayev (FPL, 2018)

A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA. - Leandro de Souza Rosa; Aravind Dasu; Pedro C. Diniz; Vanderlei Bonato (J. Signal Process. Syst., 2018)

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Sergey Gribok; et al. (FCCM, 2019)

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Debbie Marr; et al. (FPGA, 2019)

Automatic Compiler Based FPGA Accelerator for CNN Training. - Shreyas Kolala Venkataramanaiah; Yufei Ma 002; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-sun Seo (FPL, 2019)

IP Cores for Graph Kernels on FPGAs. - Sanmukh R. Kuppannagari; Rachit Rajat; Rajgopal Kannan; Aravind Dasu; Viktor K. Prasanna (HPEC, 2019)

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. - Shreyas K. Venkataramanaiah; Han-Sok Suh; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-Sun Seo (ICCAD, 2020)

DO-GPU: Domain Optimizable Soft GPUs. - Rui Ma; Jia-Ching Hsu; Tian Tan 007; Eriko Nurvitadhi; Rajesh Vivekanandham; Aravind Dasu; Martin Langhammer; Derek Chiou (FPL, 2021)

FlexScore: Quantifying Flexibility. - Tian Tan 007; Eriko Nurvitadhi; Aravind Dasu; Martin Langhammer; Derek Chiou (IEEE Comput. Archit. Lett., 2021)

Specializing FGPU for Persistent Deep Learning. - Rui Ma; Jia-Ching Hsu; Tian Tan 007; Eriko Nurvitadhi; David Sheffield; Rob Pelt; Martin Langhammer; Jaewoong Sim; Aravind Dasu; Derek Chiou (ACM Trans. Reconfigurable Technol. Syst., 2021)