SAT: A new application mapping method for power optimization in 2D - NoC. - Aravindhan Alagarsamy; Lakshminaraynan Gopalakrishnan (VDAT, 2016)

A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption. - Aravindhan Alagarsamy; Gopalakrishnan Lakshminarayanan; Sundarakannan Mahilmaran; Seok-Bum Ko (IEEE Access, 2019)

KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC. - Aravindhan Alagarsamy; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (IET Comput. Digit. Tech., 2019)

High Speed Approximate Carry Speculative Adder in Error Tolerance Applications. - Ajay Kumar Gottem; Arunmetha Sundaramoorthy; Aravindhan Alagarsamy (Int. J. Comput., 2022)

FRDS: An efficient unique on-Chip interconnection network architecture. - Aravindhan Alagarsamy; Sundarakannan Mahilmaran; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (Integr., 2022)

Design and analysis of text document clustering using salp swarm algorithm. - Muruganantham Ponnusamy; Pradeep Bedi; Tamilarasi Suresh; Aravindhan Alagarsamy; R. Manikandan; Natarajan Yuvaraj 001 (J. Supercomput., 2022)

SMA: A constructive partitioning based mapping approach for Networks-on-Chip. - Aravindhan Alagarsamy; Sundarakannan Mahilmaran; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (Microprocess. Microsystems, 2022)

SaHNoC: an optimal energy efficient hybrid networks-on-chip architecture. - Aravindhan Alagarsamy; Sundarakannan Mahilmaran; Gopalakrishnan Lakshminarayanan; Seok-Bum Ko (J. Supercomput., 2023)

Probability-based mapping approach for an application-aware networks-on-chip architectures. - Deepa Perumal; Aravindhan Alagarsamy; Sundarakannan Mahilmaran; Gian Carlo Cardarilli; Seok-Bum Ko (Nano Commun. Networks, 2024)

Design and implementation of hybrid (radix-8 Booth and TRAM) approximate multiplier using 15-4 approximate compressors for image processing application. - Srikanth Immareddy; Arunmetha Sundaramoorthy; Aravindhan Alagarsamy (J. Real Time Image Process., 2024)

A Constructive High-Speed Crypto-mining Approach with Dual SHA-256 on an FPGA. - Velamala Pavan Kumar; Aravindhan Alagarsamy (VLSID, 2025)

Reliable Synchronous and Asynchronous Counter Design in QCA. - Y. S. S. Gowri Sai Saketha; Aravindhan Alagarsamy; Marshal Raj; Gian Carlo Cardarilli; Seok-Bum Ko (J. Circuits Syst. Comput., 2025)