A fast, predictable FPGA with PLLs, dual port SRAMs and active repeaters. - Paul T. Sasaki; Yogendra Bobra; Warren E. Cory; Atul V. Cihia; Suresh M; Menon; Madhavi Kola; Mammen Thomas; Prasad Rau; Arch Zaliznyak (CICC, 1999)

Multi-protocol embedded PCS IP in a FPGA-SOC. - Ramanand Venkata; Vinson Chan; Binh Ton; Chong Lee; Huy Ngo; Malik Kabani; Tam Nguyen; Arch Zaliznyak; Ning Xue; Steven Shen; Michael Zheng; Michael Lai; et al. (CICC, 2005)

Chip Package Co-design and Physical Verification for Heterogeneous Integration. - Rajsaktish Sankaranarayanan; Archanna Srinivasan; Arch Zaliznyak; Sreelekha Mittai (ISQED, 2021)