Analysis of Bang-bang CDR circuits with equations of linear motion. - Archit Joshi (ICECS, 2008)

Period Jitter of Frequency-Locked Loops. - Archit Joshi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Bandwidth Compensation Technique for Digital PLL. - Archit Joshi; Gagan Midha (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Nonlinearity Estimation for Compensation of Phase Interpolator in Bang-Bang CDRs. - Archit Joshi; Mukul Sarkar (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An Odd Phase CDR With Phase Interpolator Trimming. - Archit Joshi; Mukul Sarkar (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Low-Pass Filter Bandwidth Adaptation Technique for Phase Interpolators. - Archit Joshi; Mukul Sarkar (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Data Path Nonlinearity Estimation for 200 Gbps PAM4 Serdes Receivers. - Archit Joshi (IEEE Access, 2024)

Nonlinearity Analysis of Down-Sampled Paths in High-Speed ADC-Based SerDes Receivers. - Archit Joshi (IEEE Access, 2025)

VERITAS: Verification and Explanation of Realness in Images for Transparency in AI Systems. - Aadi Srivastava; Vignesh Natarajkumar; Utkarsh Bheemanaboyna; Devisree Akashapu; Nagraj Gaonkar; Archit Joshi (CoRR, 2025)