Modeling Cache Effects at the Transaction Level. - Ardavan Pedram; David Craven; Andreas Gerstlauer (IESS, 2009)

A high-performance, low-power linear algebra core. - Ardavan Pedram; Andreas Gerstlauer; Robert A. van de Geijn (ASAP, 2011)

A Linear Algebra Core Design for Efficient Level-3 BLAS. - Ardavan Pedram; Syed Zohaib Gilani; Nam Sung Kim; Robert A. van de Geijn; Michael J. Schulte; Andreas Gerstlauer (ASAP, 2012)

On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators. - Ardavan Pedram; Andreas Gerstlauer; Robert A. van de Geijn (SBAC-PAD, 2012)

Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures. - Ardavan Pedram; Robert A. van de Geijn; Andreas Gerstlauer (IEEE Trans. Computers, 2012)

Floating Point Architecture Extensions for Optimized Matrix Factorization. - Ardavan Pedram; Andreas Gerstlauer; Robert A. van de Geijn (IEEE Symposium on Computer Arithmetic, 2013)

Transforming a linear algebra core to an FFT accelerator. - Ardavan Pedram; John D. McCalpin; Andreas Gerstlauer (ASAP, 2013)

Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics. - Ardavan Pedram (IPDPS Workshops, 2013)

Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator. - Ardavan Pedram; Andreas Gerstlauer; Robert A. van de Geijn (IEEE Trans. Computers, 2014)

A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores. - Ardavan Pedram; John D. McCalpin; Andreas Gerstlauer (J. Signal Process. Syst., 2014)

Deep compression and EIE: Efficient inference engine on compressed deep neural network. - Song Han 003; Xingyu Liu 001; Huizi Mao; Jing Pu; Ardavan Pedram; Mark Horowitz; Bill Dally (Hot Chips Symposium, 2016)

EIE: Efficient Inference Engine on Compressed Deep Neural Network. - Song Han 003; Xingyu Liu 001; Huizi Mao; Jing Pu; Ardavan Pedram; Mark A. Horowitz; William J. Dally (ISCA, 2016)

Improving energy efficiency of DRAM by exploiting half page row access. - Heonjae Ha; Ardavan Pedram; Stephen Richardson; Shahar Kvatinsky; Mark Horowitz (MICRO, 2016)

Evaluating programmable architectures for imaging and vision applications. - Artem Vasilyev; Nikhil Bhagdikar; Ardavan Pedram; Stephen Richardson; Shahar Kvatinsky; Mark Horowitz (MICRO, 2016)

Simulator calibration for accelerator-rich architecture studies. - Mochamad Asri; Ardavan Pedram; Lizy K. John; Andreas Gerstlauer (SAMOS, 2016)

A Systematic Approach to Blocking Convolutional Neural Networks. - Xuan Yang; Jing Pu; Blaine Burton Rister; Nikhil Bhagdikar; Stephen Richardson; Shahar Kvatinsky; Jonathan Ragan-Kelley; Ardavan Pedram; Mark Horowitz (CoRR, 2016)

CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks. - Yuanfang Li; Ardavan Pedram (ASAP, 2017)

Plasticine: A Reconfigurable Architecture For Parallel Paterns. - Raghu Prabhakar; Yaqi Zhang 001; David Koeplinger; Matthew Feldman; Tian Zhao 001; Stefan Hadjis; Ardavan Pedram; Christos Kozyrakis; Kunle Olukotun (ISCA, 2017)

Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. - Ardavan Pedram; Stephen Richardson; Mark Horowitz; Sameh Galal; Shahar Kvatinsky (IEEE Des. Test, 2017)

Spatial: a language and compiler for application accelerators. - David Koeplinger; Matthew Feldman; Raghu Prabhakar; Yaqi Zhang 001; Stefan Hadjis; Ruben Fiszel; Tian Zhao 001; Luigi Nardi; Ardavan Pedram; Christos Kozyrakis; Kunle Olukotun (PLDI, 2018)

Plasticine: A Reconfigurable Accelerator for Parallel Patterns. - Raghu Prabhakar; Yaqi Zhang 001; David Koeplinger; Matthew Feldman; Tian Zhao 001; Stefan Hadjis; Ardavan Pedram; Christos Kozyrakis; Kunle Olukotun (IEEE Micro, 2018)

Campfire: Compressible, Regularization-Free, Structured Sparse Training for Hardware Accelerators. - Noah Gamboa; Kais Kudrolli; Anand Dhoot; Ardavan Pedram (CoRR, 2020)

Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators. - Hamzah Abdel-Aziz; Ali Shafiee; Jong Hoon Shin; Ardavan Pedram; Joseph Hassoun (MLSys, 2021)

Design Space Exploration of Sparse Accelerators for Deep Neural Networks. - Jong Hoon Shin; Ali Shafiee; Ardavan Pedram; Hamzah Abdel-Aziz; Ling Li; Joseph Hassoun (CoRR, 2021)

Griffin: Rethinking Sparse Optimization for Deep Learning Architectures. - Jong Hoon Shin; Ali Shafiee; Ardavan Pedram; Hamzah Abdel-Aziz; Ling Li; Joseph Hassoun (HPCA, 2022)

Algorithm/architecture solutions to improve beyond uniform quantization in embedded DNN accelerators. - Ardavan Pedram; Ali Shafiee Ardestani; Ling Li; Hamzah Abdel-Aziz; Jun Fang; Joseph Hassoun (J. Syst. Archit., 2022)

Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network. - Song Han 003; Xingyu Liu 001; Huizi Mao; Jing Pu; Ardavan Pedram; Mark A. Horowitz; William J. Dally (CoRR, 2023)

DFModel: Design Space Optimization of Large-Scale Systems Exploiting Dataflow Mappings. - Sho Ko; Nathan Zhang; Olivia Hsu; Ardavan Pedram; Kunle Olukotun (CoRR, 2024)