Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU. - Ardhendu Sarkar; Kinjal Ray; Debaroti Chowdhury; Kishan Sahu; Solanki Kundu; Surajeet Ghosh (TENCON, 2019)

An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment. - Ardhendu Sarkar; Som Banerjee; Surajeet Ghosh (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment. - Ardhendu Sarkar; Surajeet Ghosh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA. - Ardhendu Sarkar; Sriparna Mandal; Surajeet Ghosh (ISVLSI, 2025)