Bits, Flips and RISCs. - Nicolas Gerlin; Endri Kaja; Fabian Vargas 001; Li Lu; Anselm Breitenreiter; Junchao Chen 001; Markus Ulbricht 002; Maribel Gomez; Ares Tahiraga; Sebastian Prebeck; Eyck Jentzsch; Milos Krstic; et al. (DDECS, 2023)

An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs. - Endri Kaja; Nicolas Gerlin; Jad Al Halabi; Ares Tahiraga; Sebastian Prebeck; Dominik Stoffel; Wolfgang Kunz; Wolfgang Ecker (DFT, 2024)

Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V. - Endri Kaja; Nicolas Gerlin; Ares Tahiraga; Jad Al Halabi; Sebastian Prebeck; Dominik Stoffel; Wolfgang Kunz; Wolfgang Ecker (DFT, 2024)

Implementation of Dynamic SISD-SIMD Integer Dividers. - Gianluca Radi; Ares Tahiraga; Robert Kunzelmann; Ties Jan Henderikus Kluter; Wolfgang Ecker (DDECS, 2025)