A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction. - Amir Ehsani Zonouz; Mehrdad Seyrafi; Arghavan Asad; Mohsen Soryani; Mahmood Fathy; Reza Berangi (DSD, 2009)

Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips. - Arghavan Asad; Amir Ehsani Zonouz; Mehrdad Seyrafi; Mohsen Soryani; Mahmood Fathy (ReConFig, 2009)

Design considerations to affect on shielding effectiveness for conductive enclosure. - Asghar Keshtkar; Amir Maghoul; Ali Kalantarnia; Arghavan Asad (IEICE Electron. Express, 2011)

Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors. - Arghavan Asad; Ozcan Ozturk 001; Mahmood Fathy; Mohammad Reza Jahed-Motlagh (DSD, 2015)

Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach. - Salman Onsori; Arghavan Asad; Özcan Özturk 001; Mahmood Fathy (IGSC, 2015)

Lighting the Dark-Silicon 3D Chip Multi-processors by Exploiting Heterogeneity in Cache Hierarchy. - Ashkan Sadeghi; Kaamran Raahemifar; Mahmood Fathy; Arghavan Asad (MCSoC, 2015)

Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. - Sobhan Niknam; Arghavan Asad; Mahmood Fathy; Amir-Mohammad Rahmani (ReCoSoC, 2015)

High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model. - Salman Onsori; Arghavan Asad; Kaamran Raahemifar; Mahmood Fathy (ISCAS, 2016)

UCA: An Energy-efficient Hybrid Uncore Architecture in 3D Chip-Multiprocessors to minimize crosstalk. - Pooneh Safayenikoo; Arghavan Asad; Kaamran Raahemifar; Mahmood Fathy (NoCArc@MICRO, 2016)

Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs. - Pooneh Safayenikoo; Arghavan Asad; Mahmood Fathy; Farah Mohammadi 001 (CCECE, 2017)

A new traffic compression method for end-to-end memory accesses in 3D chip-multiprocessors. - Pooneh Safayenikoo; Arghavan Asad; Mahmood Fathy; Farah Mohammadi 001 (CCECE, 2017)

Optimal Placement of Heterogeneous Uncore Component in 3D Chip-Multiprocessors. - Aniseh Dorostkar; Arghavan Asad; Mahmood Fathy; Farah Mohammadi 001 (DSD, 2017)

An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors. - Pooneh Safayenikoo; Arghavan Asad; Mahmood Fathy; Farah Mohammadi 001 (ISQED, 2017)

Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure. - Fatemeh Arezoomand; Arghavan Asad; Mahdi Fazeli; Mahmood Fathy; Farah Mohammadi 001 (MCSoC, 2017)

Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors. - Fatemeh Arezoomand; Arghavan Asad; Mahdi Fazeli; Mahmood Fathy; Farah Mohammadi 001 (ReCoSoC, 2017)

Power Modeling and Runtime Performance Optimization of Power Limited Many-Core Systems Based on a Dynamic Adaptive Approach. - Arghavan Asad; Mahmood Fathy; Mohammad Reza Jahed-Motlagh; Kaamran Raahemifar (J. Low Power Electron., 2017)

Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy. - Arghavan Asad; Ozcan Ozturk 001; Mahmood Fathy; Mohammad Reza Jahed-Motlagh (Microprocess. Microsystems, 2017)

An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses. - Pooneh Safayenikoo; Arghavan Asad; Farah Mohammadi 001 (CCECE, 2018)

NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines. - Pooneh Safayenikoo; Arghavan Asad; Mahmood Fathy; Farah Mohammadi 001 (ISCAS, 2018)

Optimization-based reconfigurable approach for low-power 3D chip-multiprocessors. - Aniseh Dorostkar; Arghavan Asad; Mahmood Fathy; Farah Mohammadi 001 (LASCAS, 2018)

A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age. - Arghavan Asad; Aniseh Dorostkar; Farah Mohammadi 001 (EURASIP J. Embed. Syst., 2018)

Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors. - Furat Al-Obaidy; Arghavan Asad; Farah Mohammadi 001 (CCECE, 2019)

Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method. - Furat Al-Obaidy; Arghavan Asad; Farah Mohammadi 001 (CCECE, 2019)

An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors. - Salman Onsori; Arghavan Asad; Kaamran Raahemifar; Mahmood Fathy (CoRR, 2019)

An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors. - Arghavan Asad; Mahdi Fazeli; Mohammad Reza Jahed-Motlagh; Mahmood Fathy; Farah Mohammadi 001 (J. Circuits Syst. Comput., 2019)

Efficient Power Consumption using Hybrid Emerging Memory Technology for 3D CMPs. - Arghavan Asad; Furat Al-Obaidy; Farah Mohammadi 001 (LASCAS, 2020)

A Power-Aware Hybrid Cache for Chip-Multi Processors Based on Neural Network Prediction Technique. - Furat Al-Obaidy; Arghavan Asad; Farah A. Mohammadi (Int. J. Parallel Program., 2021)

Noise Suppression Using Gated Recurrent Units and Nearest Neighbor Filtering. - Arghavan Asad; Rupinder Kaur; Farah A. Mohammadi (CSCI, 2022)

NeuroTower: A 3D Neuromorphic Architecture with Low-Power TSVs. - Arghavan Asad; Farah A. Mohammadi (FTC (3), 2022)

Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression. - Pooneh Safayenikoo; Arghavan Asad; Mahmood Fathy (CoRR, 2022)

A Survey on Memory Subsystems for Deep Neural Network Accelerators. - Arghavan Asad; Rupinder Kaur; Farah Mohammadi 001 (Future Internet, 2022)

Godiva: green on-chip interconnection for DNNs. - Arghavan Asad; Farah A. Mohammadi (J. Supercomput., 2023)

A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks. - Rupinder Kaur; Arghavan Asad; Farah A. Mohammadi (Comput., 2024)

Machine Learning based Dynamic Overload Surge Protection System for Electrical Appliances. - Jenish Gajera; Adla Jahnavi; Nikhil Pinto; Rupinder Kaur; Arghavan Asad; Farah A. Mohammadi (ISCAS, 2025)

LLMs meet Federated Learning for Scalable and Secure IoT Management. - Yazan Otoum; Arghavan Asad; Amiya Nayak (CoRR, 2025)

Blockchain Meets Adaptive Honeypots: A Trust-Aware Approach to Next-Gen IoT Security. - Yazan Otoum; Arghavan Asad; Amiya Nayak (CoRR, 2025)

LLM-Based Threat Detection and Prevention Framework for IoT Ecosystems. - Yazan Otoum; Arghavan Asad; Amiya Nayak (CoRR, 2025)

Open-Source LLM-Driven Federated Transformer for Predictive IoV Management. - Yazan Otoum; Arghavan Asad; Ishtiaq Ahmad (CoRR, 2025)