Compact and Accurate MOST Model for Analog Circuit Hand Calculations. - Farbod Aram; Aria Eshraghi; Terri S. Fiez (ISCAS, 1994)

Asynchronus Implementation for the Add Compare Select Processor for Communication Systems. - Aria Eshraghi; Terri S. Fiez; Thomas R. Fischer (ISCAS, 1994)

Design of a new squaring function for the Viterbi algorithm. - Aria Eshraghi; Terri S. Fiez; Kel D. Winters; Thomas R. Fischer (IEEE J. Solid State Circuits, 1994)

A Nyquist-rate delta-sigma A/D converter. - Eric T. King; Aria Eshraghi; Ian Galton; Terri S. Fiez (IEEE J. Solid State Circuits, 1998)

A spurious-free delta-sigma DAC using rotated data weighted averaging. - Russell E. Radke; Aria Eshraghi; Terri S. Fiez (CICC, 1999)

A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging. - Russell E. Radke; Aria Eshraghi; Terri S. Fiez (IEEE J. Solid State Circuits, 2000)

A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz. - Uma Chilakapati; Terri S. Fiez; Aria Eshraghi (CICC, 2001)

A CMOS transconductor with 80-dB SFDR up to 10 MHz. - Uma Chilakapati; Terri S. Fiez; Aria Eshraghi (IEEE J. Solid State Circuits, 2002)

A time-interleaved parallel /ΔΣ A/D converter. - Aria Eshraghi; Terri S. Fiez (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A comparative analysis of parallel delta-sigma ADC architectures. - Aria Eshraghi; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A 192-Virtual-Receiver 77/79GHz GMSK Code-Domain MIMO Radar System-on-Chip. - Vito Giannini; Marius Goldenberg; Aria Eshraghi; James Maligeorgos; Lysander Lim; Ryan Lobo; Dave Welland; Chung-Kai Chow; Andrew Dornbusch; Tim Dupuis; Struan Vaz; Fred Rush; et al. (ISSCC, 2019)