A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. - Jafar Savoj; Kenny C.-H. Hsieh; Fu-Tai An; J. Gong; Jay Im; Xuewen Jiang; Anup P. Jose; Vassili Kireev; Siok-Wei Lim; Arianne Roldan; D. Z. Turker; Parag Upadhyaya; et al. (IEEE J. Solid State Circuits, 2013)

A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS. - Kok Lim Chan; Kee Hian Tan; Yohan Frans; Jay Im; Parag Upadhyaya; Siok-Wei Lim; Arianne Roldan; Nakul Narang; Chin Yang Koay; Hongyuan Zhao; Ken Chang (A-SSCC, 2016)

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (ISSCC, 2017)

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS. - Kok Lim Chan; Kee Hian Tan; Yohan Frans; Jay Im; Parag Upadhyaya; Siok-Wei Lim; Arianne Roldan; Nakul Narang; Chin Yang Koay; Hongyuan Zhao; Ping-Chuan Chiang; Ken Chang (IEEE J. Solid State Circuits, 2017)

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (IEEE J. Solid State Circuits, 2017)

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET. - Marc Erett; Declan Carey; James Hudner; Ronan Casey; Kevin Geary; Pedro Neto 001; Mayank Raj; Scott McLeod; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; et al. (ISSCC, 2018)

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (ISSCC, 2018)

A 112-GB/S PAM4 Transmitter in 16NM FinFET. - Kee Hian Tan; Ping-Chuan Chiang; Yipeng Wang 003; Haibing Zhao; Arianne Roldan; Hongyuan Zhao; Nakul Narang; Siok-Wei Lim; Declan Carey; Sai Lalith Chaitanya Ambatipudi; Parag Upadhyaya; Yohan Frans; et al. (VLSI Circuits, 2018)

A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET. - Marc Erett; Declan Carey; Ronan Casey; James Hudner; Kevin Geary; Ted Lee; Mayank Raj; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; Haibing Zhao; et al. (CICC, 2019)

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (IEEE J. Solid State Circuits, 2019)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)