Fast and reconfigurable packet classification engine in FPGA-based firewall. - Arief Wicaksana; Arif Sasongko (ICEEI, 2011)

Demonstration of a context-switch method for heterogeneous reconfigurable systems. - Arief Wicaksana; Alban Bourge; Olivier Muller; Frédéric Rousseau 001 (FPL, 2016)

On-board non-regression test of HLS tools targeting FPGA. - Arief Wicaksana; Adrien Prost-Boucle; Olivier Muller; Frédéric Rousseau 001; Arif Sasongko (RSP, 2016)

Prototyping dynamic task migration on heterogeneous reconfigurable systems. - Arief Wicaksana; Alban Bourge; Olivier Muller; Arif Sasongko; Frédéric Rousseau 001 (RSP, 2017)

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design. - Arief Wicaksana; Amir Charif; Caaliph Andriamisaina; Nicolas Ventroux (DASIP, 2019)

Cross-level Co-simulation and Verification of an Automatic Transmission Control on Embedded Processor. - Cinzia Bernardeschi; Andrea Domenici; Maurizio Palmieri; Sergio Saponara; Tanguy Sassolas; Arief Wicaksana; Lilia Zaourar (SEFM, 2020)

Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams. - Arif Sasongko; I. M. Narendra Kumara; Arief Wicaksana; Frédéric Rousseau 001; Olivier Muller (ACM Trans. Reconfigurable Technol. Syst., 2021)

Decoupling processor and memory hierarchy simulators for efficient design space exploration. - Fatma Jebali; Oumaima Matoussi; Arief Wicaksana; Amir Charif; Lilia Zaourar (DroneSE/RAPIDO@HiPEAC, 2022)