A Design Methodology for the Next Generation Real-Time Vision Processors. - Jones Yudi Mori; André Werner 001; Arij Shallufa; Florian Fricke; Michael Hübner 001 (ARC, 2016)

IP Core Identification in FPGA Configuration Files using Machine Learning Techniques. - Safdar Mahmood; Jens Rettkowski; Arij Shallufa; Michael Hübner 001; Diana Göhringer (ICCE-Berlin, 2019)

Inspection of Partial Bitstreams for FPGAs Using Artificial Neural Networks. - Jens Rettkowski; Safdar Mahmood; Arij Shallufa; Michael Hübner 001; Diana Göhringer (IPDPS Workshops, 2019)