Arijit Banerjee

According to our database, Arijit Banerjee authored at least 5 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2019

A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications.

Arijit Banerjee, Benton H. Calhoun

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2018

Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications.

Arijit Banerjee, Sumanth Kamineni, Benton H. Calhoun

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2017

A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.

Arijit Banerjee, Ningxi Liu, Harsh N. Patel, Benton H. Calhoun, John W. Poulton, C. Thomas Gray

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2015

A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations.

Arijit Banerjee, Jacob Breiholz, Benton H. Calhoun

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs.

Arijit Banerjee, Mahmut E. Sinangil, John W. Poulton, C. Thomas Gray, Benton H. Calhoun

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014