Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. - Saibal Mukhopadhyay; Arijit Raychowdhury; Kaushik Roy 001 (DAC, 2003)

Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. - Arijit Raychowdhury; Saibal Mukhopadhyay; Kaushik Roy 001 (ICCAD, 2003)

Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. - Swarup Bhunia; Arijit Raychowdhury; Kaushik Roy 001 (DATE, 2004)

First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. - Swarup Bhunia; Hamid Mahmoodi-Meimand; Arijit Raychowdhury; Kaushik Roy 001 (DFT, 2004)

A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. - Arijit Raychowdhury; Kaushik Roy 001 (ICCAD, 2004)

Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies. - Myeong-Eun Hwang; Arijit Raychowdhury; Kaushik Roy 001 (ISCAS (3), 2004)

Device optimization for ultra-low power digital sub-threshold operation. - Bipul Chandra Paul; Arijit Raychowdhury; Kaushik Roy 001 (ISLPED, 2004)

A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. - Arijit Raychowdhury; Kaushik Roy 001 (ISMVL, 2004)

Modeling and Estimation of Leakage in Sub-90nm Devices. - Arijit Raychowdhury; Saibal Mukhopadhyay; Kaushik Roy 001 (VLSI Design, 2004)

A circuit-compatible model of ballistic carbon nanotube field-effect transistors. - Arijit Raychowdhury; Saibal Mukhopadhyay; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. - Saibal Mukhopadhyay; Arijit Raychowdhury; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (Asian Test Symposium, 2005)

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. - Swarup Bhunia; Hamid Mahmoodi-Meimand; Arijit Raychowdhury; Kaushik Roy 001 (DATE, 2005)

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. - Arijit Raychowdhury; Swaroop Ghosh; Swarup Bhunia; Debjyoti Ghosh; Kaushik Roy 001 (ETS, 2005)

A Feasibility Study of Subthreshold SRAM Across Technology Generations. - Arijit Raychowdhury; Saibal Mukhopadhyay; Kaushik Roy 001 (ICCD, 2005)

A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. - Arijit Raychowdhury; Swaroop Ghosh; Kaushik Roy 001 (IOLTS, 2005)

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. - Swarup Bhunia; Arijit Raychowdhury; Kaushik Roy 001 (J. Electron. Test., 2005)

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. - Swarup Bhunia; Arijit Raychowdhury; Kaushik Roy 001 (J. Electron. Test., 2005)

Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. - Saibal Mukhopadhyay; Arijit Raychowdhury; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies. - Myeong-Eun Hwang; Arijit Raychowdhury; Kairshik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. - Arijit Raychowdhury; Bipul Chandra Paul; Swarup Bhunia; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Integrated MEMS Switches for Leakage Control of Battery Operated Systems. - Arijit Raychowdhury; Jeong-Il Kim; Dimitrios Peroulis; Kaushik Roy 001 (CICC, 2006)

A high density, carbon nanotube capacitor for decoupling applications. - Mark M. Budnik; Arijit Raychowdhury; Aditya Bansal; Kaushik Roy 001 (DAC, 2006)

Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. - Arijit Raychowdhury; Bipul Chandra Paul; Swarup Bhunia; Kaushik Roy 001 (DATE, 2006)

Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. - Swaroop Ghosh; Swarup Bhunia; Arijit Raychowdhury; Kaushik Roy 001 (IOLTS, 2006)

Analysis of super cut-off transistors for ultralow power digital logic circuits. - Arijit Raychowdhury; Xuanyao Fong; Qikai Chen; Kaushik Roy 001 (ISLPED, 2006)

Leakage Power Analysis and Reduction for Nanoscale Circuits. - Amit Agarwal 001; Saibal Mukhopadhyay; Arijit Raychowdhury; Kaushik Roy 001; Chris H. Kim (IEEE Micro, 2006)

A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. - Swaroop Ghosh; Swarup Bhunia; Arijit Raychowdhury; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. - Arijit Raychowdhury; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. - Nilanjan Banerjee; Arijit Raychowdhury; Kaushik Roy 001; Swarup Bhunia; Hamid Mahmoodi (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits. - Arijit Raychowdhury; Kaushik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. - Swarup Bhunia; Hamid Mahmoodi; Arijit Raychowdhury; Kaushik Roy 001 (J. Electron. Test., 2008)

PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. - Charles Augustine; Arijit Raychowdhury; Yunfei Gao; Mark S. Lundstrom; Kaushik Roy 001 (ISQED, 2009)

A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS. - Y. William Li; Hasnain Lakdawala; Arijit Raychowdhury; Greg Taylor; Krishnamurthy Soumyanath (ISSCC, 2009)

A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process. - Hasnain Lakdawala; Y. William Li; Arijit Raychowdhury; Greg Taylor; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2009)

Resilient design in scaled CMOS for energy efficiency. - James W. Tschanz; Keith A. Bowman; Muhammad M. Khellah; Chris Wilkerson; Bibiche M. Geuskens; Dinesh Somasekhar; Arijit Raychowdhury; Jaydeep Kulkarni; Carlos Tokunaga; Shih-Lien Lu; Tanay Karnik; Vivek De (ASP-DAC, 2010)

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek De (CICC, 2010)

Resilient microprocessor design for high performance & energy efficiency. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISLPED, 2010)

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. - Arijit Raychowdhury; Bibiche M. Geuskens; Jaydeep Kulkarni; James W. Tschanz; Keith A. Bowman; Tanay Karnik; Shih-Lien Lu; Vivek De; Muhammad M. Khellah (ISSCC, 2010)

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. - James W. Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISSCC, 2010)

Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration. - Minki Cho; Nikhil Sathe; Arijit Raychowdhury; Saibal Mukhopadhyay (ITC, 2010)

Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective. - Sumeet Kumar Gupta; Arijit Raychowdhury; Kaushik Roy 001 (Proc. IEEE, 2010)

Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. - Bipul C. Paul; Arijit Raychowdhury (Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011)

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. - Arijit Raychowdhury; Jim Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek K. De (IEEE J. Solid State Circuits, 2011)

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. - Arijit Raychowdhury; Bibiche M. Geuskens; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Tanay Karnik; Muhammad M. Khellah; Vivek K. De (IEEE J. Solid State Circuits, 2011)

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS. - Arijit Raychowdhury; Carlos Tokunaga; Willem Marco Beltman; Michael Deisher; James W. Tschanz; Vivek De (CICC, 2012)

Design for test and reliability in ultimate CMOS. - Michael Nicolaidis; Lorena Anghel; Nacer-Eddine Zergainoh; Yervant Zorian; Tanay Karnik; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Carlos Tokunaga; Arijit Raychowdhury; Muhammad M. Khellah; Jaydeep Kulkarni; et al. (DATE, 2012)

TapeCache: a high density, energy efficient cache based on domain wall memory. - Rangharajan Venkatesan; Vivek Joy Kozhikkottu; Charles Augustine; Arijit Raychowdhury; Kaushik Roy 001; Anand Raghunathan (ISLPED, 2012)

A fully-digital phase-locked low dropout regulator in 32nm CMOS. - Arijit Raychowdhury; Dinesh Somasekhar; James W. Tschanz; Vivek De (VLSIC, 2012)

Spin torque devices in embedded memory: model studies and design space exploration. - Arijit Raychowdhury (ICCAD, 2013)

Beyond charge based computation: Design space exploration of spin transfer torque based MRAMs for embedded applications. - Arijit Raychowdhury (ISLPED, 2013)

Pulsed READ in spin transfer torque (STT) memory bitcell for lower READ disturb. - Arijit Raychowdhury (NANOARCH, 2013)

Introduction to the special issue on memory technologies. - Bipul C. Paul; Arijit Raychowdhury (ACM J. Emerg. Technol. Comput. Syst., 2013)

A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS. - Arijit Raychowdhury; Carlos Tokunaga; Willem Marco Beltman; Michael Deisher; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2013)

Neuro Inspired Computing with Coupled Relaxation Oscillators. - Suman Datta; Nikhil Shukla; Matthew Cotter; Abhinav Parihar; Arijit Raychowdhury (DAC, 2014)

Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads. - Samantak Gangopadhyay; Youngtak Lee; Saad Bin Nasir; Arijit Raychowdhury (DATE, 2014)

The role of adaptation and resiliency in computation and power management. - Arijit Raychowdhury; Saad Bin Nasir; Samantak Gangopadhyay (ICCAD, 2014)

Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators. - Saad Bin Nasir; Youngtak Lee; Arijit Raychowdhury (ISQED, 2014)

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. - Carlos Tokunaga; Joseph F. Ryan 002; Charles Augustine; Jaydeep P. Kulkarni; Yi-Chun Shih; Stephen T. Kim; Rinkle Jain; Keith A. Bowman; Arijit Raychowdhury; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2014)

Exploiting Synchronization Properties of Correlated Electron Devices in a Non-Boolean Computing Fabric for Template Matching. - Abhinav Parihar; Nikhil Shukla; Suman Datta; Arijit Raychowdhury (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits. - Samantak Gangopadhyay; Dinesh Somasekhar; James W. Tschanz; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2014)

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays. - Ashwin Chintaluri; Abhinav Parihar; Suriyaprakash Natarajan; Helia Naeimi; Arijit Raychowdhury (ATS, 2015)

Session 6 - Analog circuits using digital cells. - Jing Yang; Arijit Raychowdhury (CICC, 2015)

Integrated power management in IoT devices under wide dynamic ranges of operation. - Samantak Gangopadhyay; Saad Bin Nasir; Arijit Raychowdhury (DAC, 2015)

5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range. - Saad Bin Nasir; Samantak Gangopadhyay; Arijit Raychowdhury (ISSCC, 2015)

A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends. - Anvesha Amaravati; Manan Chugh; Arijit Raychowdhury (VLSI-SoC, 2015)

A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends. - Anvesha Amaravati; Manan Chugh; Arijit Raychowdhury (VLSI-SoC (Selected Papers), 2015)

A Model Study of an All-Digital, Discrete-Time and Embedded Linear Regulator. - Saad Bin Nasir; Arijit Raychowdhury (CoRR, 2015)

Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators. - Paolo Maffezzoni; Luca Daniel; Nikhil Shukla; Suman Datta; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Ultra-Low Power, "Always-On" Camera Front-End for Posture Detection in Body Worn Cameras Using Restricted Boltzman Machines. - Soham Jayesh Desai; Mohammed Shoaib; Arijit Raychowdhury (IEEE Trans. Multi Scale Comput. Syst., 2015)

Embedded hybrid LDO topologies for digital load circuits. - Saad Bin Nasir; Arijit Raychowdhury (APCCAS, 2016)

UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction. - Samantak Gangopadhyay; Saad Bin Nasir; A. Subramanian; Visvesh Sathe 001; Arijit Raychowdhury (ESSCIRC, 2016)

A 130nm hybrid low dropout regulator based on switched mode control for digital load circuits. - Saad Bin Nasir; Shreyas Sen; Arijit Raychowdhury (ESSCIRC, 2016)

All-digital linear regulators with proactive and reactive gain-boosting for supply droop mitigation in digital load circuits. - Saad Bin Nasir; Arijit Raychowdhury (ISCAS, 2016)

A Light-powered, "Always-On", Smart Camera with Compressed Domain Gesture Detection. - Amaravati Anvesha; Shaojie Xu; Ningyuan Cao; Justin Romberg; Arijit Raychowdhury (ISLPED, 2016)

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays. - Insik Yoon; Ashwin Chintaluri; Arijit Raychowdhury (ITC, 2016)

Computing with Dynamical Systems Based on Insulator-Metal-Transition Oscillators. - Abhinav Parihar; Nikhil Shukla; Matthew Jerry; Suman Datta; Arijit Raychowdhury (CoRR, 2016)

Vertex coloring of graphs via phase dynamics of coupled oscillatory networks. - Abhinav Parihar; Nikhil Shukla; Matthew Jerry; Suman Datta; Arijit Raychowdhury (CoRR, 2016)

The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction. - Sandip Ray; Yier Jin; Arijit Raychowdhury (IEEE Des. Test, 2016)

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays. - Ashwin Chintaluri; Helia Naeimi; Suriyaprakash Natarajan; Arijit Raychowdhury (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Cache Design with Domain Wall Memory. - Rangharajan Venkatesan; Vivek Joy Kozhikkottu; Mrigank Sharad; Charles Augustine; Arijit Raychowdhury; Kaushik Roy 001; Anand Raghunathan (IEEE Trans. Computers, 2016)

Enabling New Computation Paradigms with HyperFET - An Emerging Device. - Wei-Yu Tsai; Xueqing Li 002; Matthew Jerry; Baihua Xie; Nikhil Shukla; Huichu Liu; Nandhini Chandramoorthy; Matthew Cotter; Arijit Raychowdhury; Donald M. Chiarulli; Steven P. Levitan; Suman Datta; et al. (IEEE Trans. Multi Scale Comput. Syst., 2016)

A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training. - Amaravati Anvesha; Arijit Raychowdhury (A-SSCC, 2017)

Test and Reliability of Emerging Non-volatile Memories. - Said Hamdioui; Peyman Pouyan; Huawei Li 001; Ying Wang 001; Arijit Raychowdhury; Insik Yoon (ATS, 2017)

A 65nm compressive-sensing time-based ADC with embedded classification and INL-aware training for arrhythmia detection. - Amaravati Anvesha; Shaojie Xu; Justin Romberg; Arijit Raychowdhury (BioCAS, 2017)

Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. - Samantak Gangopadhyay; Saad Bin Nasir; Hoan Nguyen; Jihoon Jeong; Francois Atallah; Keith A. Bowman; Arijit Raychowdhury (CICC, 2017)

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. - Suman Datta; Alan C. Seabaugh; Michael T. Niemier; Arijit Raychowdhury; Darrell Schlom; Debdeep Jena; Huili Grace Xing; H.-S. Philip Wong; Eric Pop; Sayeef S. Salahuddin; Sumeet Kumar Gupta; Supratik Guha (DAC, 2017)

High efficiency power side-channel attack immunity using noise injection in attenuated signature domain. - Debayan Das; Shovan Maity; Saad Bin Nasir; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (HOST, 2017)

Appearance-based gesture recognition in the compressed domain. - Shaojie Xu; Anvesha Amaravati; Justin Romberg; Arijit Raychowdhury (ICASSP, 2017)

Connecting spectral techniques for graph coloring and eigen properties of coupled dynamics: A pathway for solving combinatorial optimizations (Invited paper). - Abhinav Parihar; Nikhil Shukla; Matthew Jerry; Suman Datta; Arijit Raychowdhury (ICCAD, 2017)

Collaborative intelligence in optical/IR camera based wireless sensor nodes for HVAC control. - Ningyuan Cao; Shreyas Sen; Arijit Raychowdhury (IEEE SENSORS, 2017)

Computational paradigms using oscillatory networks based on state-transition devices. - Abhinav Parihar; Nikhil Shukla; Matthew Jerry; Suman Datta; Arijit Raychowdhury (IJCNN, 2017)

Test challenges in embedded STT-MRAM arrays. - Insik Yoon; Arijit Raychowdhury (ISQED, 2017)

Innovative practices session 4A variation-tolerant design of circuits/systems. - Arijit Raychowdhury (VTS, 2017)

Stochastic IMT (insulator-metal-transition) neurons: An interplay of thermal and threshold noise at bifurcation. - Abhinav Parihar; Matthew Jerry; Suman Datta; Arijit Raychowdhury (CoRR, 2017)

Self-Optimizing IoT Wireless Video Sensor Node With In-Situ Data Analytics and Context-Driven Energy-Aware Real-Time Adaptation. - Ningyuan Cao; Saad Bin Nasir; Shreyas Sen; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations. - Insik Yoon; Muya Chang; Kai Ni 004; Matthew Jerry; Samantak Gangopadhyay; Gus Henry Smith; Tomer Hamam; Vijayakrishan Narayanan; Justin Romberg; Shih-Lien Lu; Suman Datta; Arijit Raychowdhury (DRC, 2018)

Computing with Coupled Oscillators: Theory, Devices, and Applications. - György Csaba; Arijit Raychowdhury; Suman Datta; Wolfgang Porod (ISCAS, 2018)

A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation. - Saad Bin Nasir; Anto Kavungal Davis; Mohamed Lamine Faycal Bellaredj; Madhavan Swaminathan; Arijit Raychowdhury; Adam Beece; Don Disney; Yong Wang; Hesam Fathi Moghadam; Eric Soenen; Jongku Kang; Yasuhiko Mano; et al. (ISCAS, 2018)

A 55nm time-domain mixed-signal neuromorphic accelerator with stochastic synapses and embedded reinforcement learning for autonomous micro-robots. - Anvesha Amaravati; Saad Bin Nasir; Sivaram Thangadurai; Insik Yoon; Arijit Raychowdhury (ISSCC, 2018)

NavREn-Rl: Learning to fly in real environment via end-to-end deep reinforcement learning using monocular images. - Malik Aqeel Anwar; Arijit Raychowdhury (M2VIP, 2018)

Dynamics of Coupled Systems and their Computing Properties Invited Paper : Invited Paper. - Abhinav Parihar; Anvesha Amaravati; Matthew Jerry; Suman Datta; Arijit Raychowdhury (NEWCAS, 2018)

Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits. - Saad Bin Nasir; Shreyas Sen; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2018)

Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays. - Insik Yoon; Arijit Raychowdhury (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A 130 nm 165 nJ/frame Compressed-Domain Smashed-Filter-Based Mixed-Signal Classifier for "In-Sensor" Analytics in Smart Cameras. - Anvesha Amaravati; Shaojie Xu; Justin Romberg; Arijit Raychowdhury (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity. - Debayan Das; Shovan Maity; Saad Bin Nasir; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-Off. - Saad Bin Nasir; Shreyas Sen; Arijit Raychowdhury (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Light-Powered Smart Camera With Compressed Domain Gesture Detection. - Anvesha Amaravati; Shaojie Xu; Ningyuan Cao; Justin Romberg; Arijit Raychowdhury (IEEE Trans. Circuits Syst. Video Technol., 2018)

Smart Sensing for HVAC Control: Collaborative Intelligence in Optical and IR Cameras. - Ningyuan Cao; Justin Ting; Shreyas Sen; Arijit Raychowdhury (IEEE Trans. Ind. Electron., 2018)

Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations. - Muya Chang; Li-Hsiang Lin; Justin Romberg; Arijit Raychowdhury (CICC, 2019)

A 55nm 50nJ/encode 13nJ/decode Homomorphic Encryption Crypto-Engine for IoT Nodes to Enable Secure Computation on Encrypted Data. - Insik Yoon; Ningyuan Cao; Anvesha Amaravati; Arijit Raychowdhury (CICC, 2019)

Rebooting Our Computing Models. - Patsy Cadareanu; N. Reddy C; Carmen G. Almudéver; A. Khanna; Arijit Raychowdhury; Suman Datta; Koen Bertels; Vijayakrishan Narayanan; Massimiliano Di Ventra; Pierre-Emmanuel Gaillardon (DATE, 2019)

Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous Drones. - Insik Yoon; Malik Aqeel Anwar; Titash Rakshit; Arijit Raychowdhury (DATE, 2019)

Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture. - Muya Chang; Samantak Gangopadhyay; Tomer Hamam; Justin Romberg; Arijit Raychowdhury (ICASSP, 2019)

Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment. - Brian Crafton; Matt West 002; Padip Basnet; Eric Vogel; Arijit Raychowdhury (ISLPED, 2019)

A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. - Francois Atallah; Keith A. Bowman; Hoan Nguyen; Jihoon Jeong; Daniel Yingling; Yu Sun; Brad Appel; Anthony Polomik; Mahesh Harinath; Joshua Morelli; Thomas Moore; Nathaniel Reeves; et al. (ISSCC, 2019)

A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics. - Ningyuan Cao; Muya Chang; Arijit Raychowdhury (ISSCC, 2019)

A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. - Keith A. Bowman; Samantak Gangopadhyay; Francois Atallah; Hoan Nguyen; Jihoon Jeong; Daniel Yingling; Anthony Polomik; Mahesh Harinath; Nathaniel Reeves; Amer Cassier; Brad Appel; Arijit Raychowdhury (VLSI Circuits, 2019)

Direct Feedback Alignment with Sparse Connections for Local Learning. - Brian Crafton; Abhinav Parihar; Evan Gebhardt; Arijit Raychowdhury (CoRR, 2019)

Design space exploration of Ferroelectric FET based Processing-in-Memory DNN Accelerator. - Insik Yoon; Matthew Jerry; Suman Datta; Arijit Raychowdhury (CoRR, 2019)

SCNIFFER: Low-Cost, Automated, EfficientElectromagnetic Side-Channel Sniffing. - Josef Danial; Debayan Das; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (CoRR, 2019)

Context-Aware Intelligence in Resource-Constrained IoT Nodes: Opportunities and Challenges. - Baibhab Chatterjee; Shreyas Sen; Ningyuan Cao; Arijit Raychowdhury (IEEE Des. Test, 2019)

Guest Editors' Introduction: Intelligent Resource-Constrained Sensor Nodes. - Shreyas Sen; Arijit Raychowdhury; Shih-Lien Lu (IEEE Des. Test, 2019)

Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones. - Insik Yoon; Malik Aqeel Anwar; Rajiv V. Joshi; Titash Rakshit; Arijit Raychowdhury (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

X-DeepSCA: Cross-Device Deep Learning Side Channel Attack. - Debayan Das; Anupam Golder; Josef Danial; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (IACR Cryptol. ePrint Arch., 2019)

A 55-nm, 1.0-0.4V, 1.25-pJ/MAC Time-Domain Mixed-Signal Neuromorphic Accelerator With Stochastic Synapses for Reinforcement Learning in Autonomous Mobile Robots. - Anvesha Amaravati; Saad Bin Nasir; Justin Ting; Insik Yoon; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2019)

Computing With Networks of Oscillatory Dynamical Systems. - Arijit Raychowdhury; Abhinav Parihar; Gus Henry Smith; Vijaykrishnan Narayanan; György Csaba; Matthew Jerry; Wolfgang Porod; Suman Datta (Proc. IEEE, 2019)

Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack. - Anupam Golder; Debayan Das; Josef Danial; Santosh Ghosh; Shreyas Sen; Arijit Raychowdhury (IEEE Trans. Very Large Scale Integr. Syst., 2019)

XBAROPT - Enabling Ultra-Pipelined, Novel STT MRAM Based Processing-in-Memory DNN Accelerator. - Aqeel Anwar; Arijit Raychowdhury; Ryan Hatcher; Titash Rakshit (AICAS, 2020)

Learning to Walk: Spike Based Reinforcement Learning for Hexapod Robot Central Pattern Generation. - Ashwin Sanjay Lele; Yan Fang; Justin Ting; Arijit Raychowdhury (AICAS, 2020)

Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS. - Debayan Das; Josef Danial; Anupam Golder; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (CICC, 2020)

Bio-inspired Gait Imitation of Hexapod Robot Using Event-Based Vision Sensor and Spiking Neural Network. - Justin Ting; Yan Fang; Ashwin Sanjay Lele; Arijit Raychowdhury (IJCNN, 2020)

A Quad-Output Elastic Switched Capacitor Converter and Per-Core LDO with 87% Power Efficiency and 2.5× Core-Frequency Range Improvement. - Samantak Gangopadhyay; James W. Tschanz; Arijit Raychowdhury (ISCAS, 2020)

Hardware-Aware Pruning of DNNs using LFSR-Generated Pseudo-Random Indices. - Foroozan Karimzadeh; Ningyuan Cao; Brian Crafton; Justin Romberg; Arijit Raychowdhury (ISCAS, 2020)

27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. - Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash Varna 001; Harish Krishnamurthy; Sanu Mathew; Santosh Ghosh; et al. (ISSCC, 2020)

31.1 A 65nm 8.79TOPS/W 23.82mW Mixed-Signal Oscillator-Based NeuroSLAM Accelerator for Applications in Edge Robotics. - Jong-Hyeok Yoon; Arijit Raychowdhury (ISSCC, 2020)

Non-isolated 48V-to-1V Heterogeneous Integrated Voltage Converters for High Performance Computing in Data Centers. - Minxiang Gong; Xin Zhang 025; Arijit Raychowdhury (MWSCAS, 2020)

Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. - Brian Crafton; Samuel Spetalnick; Gauthaman Murali; Tushar Krishna; Sung Kyu Lim; Arijit Raychowdhury (VLSI-SOC, 2020)

Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. - Brian Crafton; Samuel Spetalnick; Gauthaman Murali; Tushar Krishna; Sung Kyu Lim; Arijit Raychowdhury (VLSI-SoC (Selected Papers), 2020)

Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR Indexing. - Foroozan Karimzadeh; Arijit Raychowdhury (VLSI-SOC, 2020)

Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion. - Ashwin Sanjay Lele; Yan Fang; Justin Ting; Arijit Raychowdhury (VLSI-SOC, 2020)

A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. - Rakshith Saligram; Ankit Kaul; Muhannad S. Bakir; Arijit Raychowdhury (VLSI-SOC, 2020)

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication. - Rakshith Saligram; Ankit Kaul; Muhannad S. Bakir; Arijit Raychowdhury (VLSI-SoC (Selected Papers), 2020)

A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller. - Ningyuan Cao; Baibhab Chatterjee; Minxiang Gong; Muya Chang; Shreyas Sen; Arijit Raychowdhury (VLSI Circuits, 2020)

Autonomous Navigation via Deep Reinforcement Learning for Resource Constraint Edge Nodes Using Transfer Learning. - Aqeel Anwar; Arijit Raychowdhury (IEEE Access, 2020)

SCNIFFER: Low-Cost, Automated, Efficient Electromagnetic Side-Channel Sniffing. - Josef Danial; Debayan Das; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (IEEE Access, 2020)

Counting Cards: Exploiting Weight and Variance Distributions for Robust Compute In-Memory. - Brian Crafton; Samuel Spetalnick; Arijit Raychowdhury (CoRR, 2020)

Masked Face Recognition for Secure Authentication. - Aqeel Anwar; Arijit Raychowdhury (CoRR, 2020)

A Survey of FPGA-Based Robotic Computing. - Zishen Wan; Bo Yu 014; Thomas Yuang Li; Jie Tang 003; Yuhao Zhu 001; Yu Wang; Arijit Raychowdhury; Shaoshan Liu (CoRR, 2020)

Learning to Walk: Bio-Mimetic Hexapod Locomotion via Reinforcement-Based Spiking Central Pattern Generation. - Ashwin Sanjay Lele; Yan Fang; Justin Ting; Arijit Raychowdhury (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

120.147 Efficient Electromagnetic Side Channel Analysis by Probe Positioning using Multi-Layer Perceptron. - Anupam Golder; Baogeng Ma; Debayan Das; Josef Danial; Shreyas Sen; Arijit Raychowdhury (IACR Cryptol. ePrint Arch., 2020)

A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics. - Ningyuan Cao; Muya Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2020)

OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers. - Muya Chang; Li-Hsiang Lin; Justin Romberg; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2020)

FerroElectronics for Edge Intelligence. - Ali Keshavarzi; Kai Ni 004; Wilbert van den Hoek; Suman Datta; Arijit Raychowdhury (IEEE Micro, 2020)

Hardware-Algorithm Co-Design Enabling Efficient Event-based Object Detection. - Brian Crafton; Andrew Paredes; Evan Gebhardt; Arijit Raychowdhury (AICAS, 2021)

iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform. - Tian Gao; Zishen Wan; Yuyang Zhang; Bo Yu 014; Yanjun Zhang; Shaoshan Liu; Arijit Raychowdhury (AICAS, 2021)

An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform. - Zishen Wan; Yuyang Zhang; Arijit Raychowdhury; Bo Yu 014; Yanjun Zhang; Shaoshan Liu (AICAS, 2021)

Merged Logic and Memory Fabrics for AI Workloads. - Brian Crafton; Samuel Spetalnick; Arijit Raychowdhury (ASP-DAC, 2021)

CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. - Brian Crafton; Samuel Spetalnick; Jong-Hyeok Yoon; Wei Wu; Carlos Tokunaga; Vivek De; Arijit Raychowdhury (A-SSCC, 2021)

CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications. - Rakshith Saligram; Suman Datta; Arijit Raychowdhury (CICC, 2021)

A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance. - Rakshith Saligram; Divya Prasad; David Pietromonaco; Arijit Raychowdhury; Brian Cline (CICC, 2021)

A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (CICC, 2021)

Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems. - Zishen Wan; Aqeel Anwar; Yu-Shun Hsiao; Tianyu Jia; Vijay Janapa Reddi; Arijit Raychowdhury (DAC, 2021)

Statistical Optimization of Compute In-Memory Performance Under Device Variation. - Brian Crafton; Samuel Spetalnick; Jong-Hyeok Yoon; Arijit Raychowdhury (ISLPED, 2021)

Automatic Generation of Translators for Packet-Based and Emerging Protocols. - Brian Crafton; Arijit Raychowdhury; Sung Kyu Lim (ISQED, 2021)

F4: Electronics for a Quantum World. - Edoardo Charbon; Alicia Klinefelter; Massimo Alioto; Yao-Hong Liu; Munehiko Nagatani; Arijit Raychowdhury; Andreia Cathelin; Boris Murmann (ISSCC, 2021)

F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology. - Nick Van Helleputte; Arijit Raychowdhury; Ping-Hsuan Hsieh; Jun Deguchi; Matteo Perenzoni; Esther Rodríguez-Villegas; Long Yan; Andreia Cathelin; Keith A. Bowman; Chris Van Hoof (ISSCC, 2021)

Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee. - Arijit Raychowdhury; Mijung Noh; Keith A. Bowman (ISSCC, 2021)

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2021)

A decentralized policy gradient approach to multi-task reinforcement learning. - Sihan Zeng; Malik Aqeel Anwar; Thinh T. Doan 001; Arijit Raychowdhury; Justin Romberg (UAI, 2021)

Multi-Task Federated Reinforcement Learning with Adversaries. - Aqeel Anwar; Arijit Raychowdhury (CoRR, 2021)

MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. - Yu-Shun Hsiao; Zishen Wan; Tianyu Jia; Radhika Ghosal; Arijit Raychowdhury; David Brooks 001; Gu-Yeon Wei; Vijay Janapa Reddi (CoRR, 2021)

Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads. - Brian Crafton; Samuel Spetalnick; Yan Fang; Arijit Raychowdhury (IEEE Des. Test, 2021)

EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures. - Debayan Das; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (IEEE Des. Test, 2021)

EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. - Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash Varna 001; Harish K. Krishnamurthy; Sanu Mathew; Santosh Ghosh; et al. (IEEE J. Solid State Circuits, 2021)

NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics. - Jong-Hyeok Yoon; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2021)

A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences. - Foroozan Karimzadeh; Ningyuan Cao; Brian Crafton; Justin Romberg; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update. - Minxiang Gong; Ningyuan Cao; Muya Chang; Arijit Raychowdhury (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Robotic Computing on FPGAs: Current Progress, Research Challenges, and Opportunities. - Zishen Wan; Ashwin Sanjay Lele; Bo Yu 014; Shaoshan Liu; Yu Wang; Vijay Janapa Reddi; Cong Hao; Arijit Raychowdhury (AICAS, 2022)

Circuit and System Technologies for Energy-Efficient Edge Robotics: (Invited Paper). - Zishen Wan; Ashwin Sanjay Lele; Arijit Raychowdhury (ASP-DAC, 2022)

An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems. - Muya Chang; Xunzhao Yin; Zoltán Toroczkai; Xiaobo Hu 001; Arijit Raychowdhury (CICC, 2022)

An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems. - Qiang Liu 011; Zishen Wan; Bo Yu 014; Weizhuang Liu; Shaoshan Liu; Arijit Raychowdhury (CICC, 2022)

Improving compute in-memory ECC reliability with successive correction. - Brian Crafton; Zishen Wan; Samuel Spetalnick; Jong-Hyeok Yoon; Wei Wu; Carlos Tokunaga; Vivek De; Arijit Raychowdhury (DAC, 2022)

FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems. - Zishen Wan; Aqeel Anwar; Abdulrahman Mahmoud; Tianyu Jia; Yu-Shun Hsiao; Vijay Janapa Reddi; Arijit Raychowdhury (DATE, 2022)

Exploration into the Explainability of Neural Network Models for Power Side-Channel Analysis. - Anupam Golder; Ashwin Bhat; Arijit Raychowdhury (ACM Great Lakes Symposium on VLSI, 2022)

Analyzing and Improving Resilience and Robustness of Autonomous Systems. - Zishen Wan; Karthik Swaminathan; Pin-Yu Chen; Nandhini Chandramoorthy; Arijit Raychowdhury (ICCAD, 2022)

RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning. - Adarsh Kumar Kosta; Malik Aqeel Anwar; Priyadarshini Panda; Arijit Raychowdhury; Kaushik Roy 001 (ICRA, 2022)

Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory. - Brian Crafton; Connor Talley; Samuel Spetalnick; Jong-Hyeok Yoon; Arijit Raychowdhury (ISCAS, 2022)

Fusing Frame and Event Vision for High-speed Optical Flow for Edge Application. - Ashwin Sanjay Lele; Arijit Raychowdhury (ISCAS, 2022)

A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. - Muya Chang; Samuel D. Spetalnick; Brian Crafton; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2022)

A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. - Samuel D. Spetalnick; Muya Chang; Brian Crafton; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2022)

Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge. - Ashwin Bhat; Adou Sangbone Assoa; Arijit Raychowdhury (VLSI-SoC, 2022)

Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge Distillation. - Foroozan Karimzadeh; Arijit Raychowdhury (VLSI-SoC, 2022)

Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity. - Foroozan Karimzadeh; Arijit Raychowdhury (VLSI-SoC, 2022)

Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing. - Wriddhi Chakraborty; P. Shrestha; A. Gupta; Rakshith Saligram; Samuel Spetalnick; J. Campbell; Arijit Raychowdhury; Suman Datta (VLSI Technology and Circuits, 2022)

A 90.4% Peak Efficiency 48V/1V Three-Level Hybrid Dickson Converter with Gradient Descent Run-Time Optimizer and GaN/Si Hybrid Conversion. - Minxiang Gong; Xin Zhang 025; Arijit Raychowdhury (VLSI Technology and Circuits, 2022)

Circuit and System Technologies for Energy-Efficient Edge Robotics. - Zishen Wan; Ashwin Sanjay Lele; Arijit Raychowdhury (CoRR, 2022)

A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. - Mithilesh Kumar 008; Alak Majumder; Abir J. Mondal; Arijit Raychowdhury; Bidyut K. Bhattacharyya (Integr., 2022)

EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures. - Josef Danial; Debayan Das; Anupam Golder; Santosh Ghosh; Arijit Raychowdhury; Shreyas Sen (ACM J. Emerg. Technol. Comput. Syst., 2022)

A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller. - Ningyuan Cao; Baibhab Chatterjee; Jianbo Liu; Boyang Cheng; Minxiang Gong; Muya Chang; Shreyas Sen; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2022)

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2022)

A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2022)

An End-to-End Spiking Neural Network Platform for Edge Robotics: From Event-Cameras to Central Pattern Generation. - Ashwin Sanjay Lele; Yan Fang; Justin Ting; Arijit Raychowdhury (IEEE Trans. Cogn. Dev. Syst., 2022)

BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory. - Foroozan Karimzadeh; Jong-Hyeok Yoon; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses. - Rakshith Saligram; Suman Datta; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Practical Design-Space Analysis of Compute-in-Memory With SRAM. - Samuel Spetalnick; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Reducing Overhead of Feature Importance Visualization via Static GradCAM Computation. - Ashwin Bhat; Arijit Raychowdhury (AICAS, 2023)

PCB Identification Based on Machine Learning Utilizing Power Consumption Variability. - Anupam Golder; Arijit Raychowdhury (AICAS, 2023)

E-Track: Eye Tracking with Event Camera for Extended Reality (XR) Applications. - Nealson Li; Ashwin Bhat; Arijit Raychowdhury (AICAS, 2023)

Explainable ECG Beat Classification On The Edge for Smart, Trustworthy and Low-Power Wearables. - Ashwin Bhat; Arijit Raychowdhury (BioCAS, 2023)

A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. - Mustafa Fayez Ali; Indranil Chakraborty; Sakshi Choudhary; Muya Chang; Dong Eun Kim; Arijit Raychowdhury; Kaushik Roy 001 (CICC, 2023)

Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. - Ashwin Sanjay Lele; Muya Chang; Samuel D. Spetalnick; Brian Crafton; Arijit Raychowdhury; Yan Fang (DAC, 2023)

BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems. - Zishen Wan; Nandhini Chandramoorthy; Karthik Swaminathan; Pin-Yu Chen; Vijay Janapa Reddi; Arijit Raychowdhury (DAC, 2023)

Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving. - Kshitij Bhardwaj; Zishen Wan; Arijit Raychowdhury; Ryan A. Goldhahn (DATE, 2023)

MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. - Yu-Shun Hsiao; Zishen Wan; Tianyu Jia; Radhika Ghosal; Abdulrahman Mahmoud; Arijit Raychowdhury; David Brooks 001; Gu-Yeon Wei; Vijay Janapa Reddi (DATE, 2023)

A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems. - Adou Sangbone Assoa; Ashwin Bhat; Sigang Ryu; Arijit Raychowdhury (ACM Great Lakes Symposium on VLSI, 2023)

RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs. - Zachary J. Ellis; Anupam Golder; Addison J. Elliott; Arijit Raychowdhury (ACM Great Lakes Symposium on VLSI, 2023)

Non-Uniform Interpolation in Integrated Gradients for Low-Latency Explainable-AI. - Ashwin Bhat; Arijit Raychowdhury (ISCAS, 2023)

Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. - Ashwin Sanjay Lele; Muya Chang; Samuel Spetalnick; Yan Fang; Brian Crafton; Shota Konno; Arijit Raychowdhury (ISCAS, 2023)

Cryogenic CMOS as an Enabler for Low Power Dynamic Logic. - Rakshith Saligram; Suman Datta; Arijit Raychowdhury (ISLPED, 2023)

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. - Muya Chang; Ashwin Sanjay Lele; Samuel D. Spetalnick; Brian Crafton; Shota Konno; Zishen Wan; Ashwin Bhat; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2023)

A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications. - Sigang Ryu; Adou Sangbone Assoa; Shota Konno; Arijit Raychowdhury (VLSI Technology and Circuits, 2023)

A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. - Samuel D. Spetalnick; Muya Chang; Shota Konno; Brian Crafton; Ashwin Sanjay Lele; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (VLSI Technology and Circuits, 2023)

A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer. - Minxiang Gong; Hua Chen; Xin Zhang 025; Rinkle Jain; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2023)

Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). - Masum Hossain; Arijit Raychowdhury; Sanu K. Mathew; Yakun Sophia Shao; Yih Wang (IEEE J. Solid State Circuits, 2023)

MulBERRY: Enabling Bit-Error Robustness for Energy-Efficient Multi-Agent Autonomous Systems. - Zishen Wan; Nandhini Chandramoorthy; Karthik Swaminathan; Pin-Yu Chen; Kshitij Bhardwaj; Vijay Janapa Reddi; Arijit Raychowdhury (ASPLOS (2), 2024)

Special Session: Neuro-Symbolic Architecture Meets Large Language Models: A Memory-Centric Perspective. - Mohamed Ibrahim 002; Zishen Wan; Haitong Li; Priyadarshini Panda; Tushar Krishna; Pentti Kanerva; Yiran Chen 001; Arijit Raychowdhury (CODES+ISSS, 2024)

H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations. - Zishen Wan; Che-Kai Liu; Mohamed Ibrahim 002; Hanchen Yang; Samuel Spetalnick; Tushar Krishna; Arijit Raychowdhury (DATE, 2024)

Thinking and Moving: An Efficient Computing Approach for Integrated Task and Motion Planning in Cooperative Embodied AI Systems. - Zishen Wan; Yuhang Du; Mohamed Ibrahim 002; Yang (Katie) Zhao; Tushar Krishna; Arijit Raychowdhury (ICCAD, 2024)

A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC. - Kaushik Bhattacharyya; Minxiang Gong; Muya Chang; Xin Zhang 025; Arijit Raychowdhury (ISCAS, 2024)

Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories. - Rakshith Saligram; Amol D. Gaidhane; Yu Kevin Cao; Suman Datta; Arijit Raychowdhury (ISLPED, 2024)

Cryogenic Operation of Computing-In-Memory based Spiking Neural Network. - Laith A. Shamieh; Wei-Chun Wang; Shida Zhang; Rakshith Saligram; Amol D. Gaidhane; Yu Cao 001; Arijit Raychowdhury; Suman Datta; Saibal Mukhopadhyay (ISLPED, 2024)

Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Ritik Raj; Chaojian Li; Haoran You; Yonggan Fu; Cheng Wan 005; Ananda Samajdar; Yingyan Celine Lin; Tushar Krishna; Arijit Raychowdhury (ISPASS, 2024)

30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2024)

Accurate Low-Degree Polynomial Approximation of Non-Polynomial Operators for Fast Private Inference in Homomorphic Encryption. - Jingtian Dang; Jianming Tong; Anupam Golder; Cong Hao; Arijit Raychowdhury; Tushar Krishna (MLSys, 2024)

A 28nm Approximate / Binary 6T CAM for Sequence Alignment. - Brian Crafton; Samuel D. Spetalnick; Muya Chang; Arijit Raychowdhury (VLSI Technology and Circuits, 2024)

Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits. - Suman Datta; Eknath Sarkar; Khandker Akif Aabrar; Shan Deng; Jaewon Shin; Arijit Raychowdhury; Shimeng Yu; Asif Khan (VLSI Technology and Circuits, 2024)

A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω. - Shota Konno; Zachary J. Ellis; Anupam Golder; Sigang Ryu; Daniel Dinu; Avinash Varna 001; Sanu Mathew; Arijit Raychowdhury (VLSI Technology and Circuits, 2024)

Twofold Sparsity: Joint Bit- and Network-Level Sparsity for Energy-Efficient Deep Neural Network Using RRAM Based Compute-In-Memory. - Foroozan Karimzadeh; Arijit Raychowdhury (IEEE Access, 2024)

Towards Cognitive AI Systems: a Survey and Prospective on Neuro-Symbolic AI. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Chaojian Li; Haoran You; Yonggan Fu; Cheng Wan 005; Tushar Krishna; Yingyan Lin; Arijit Raychowdhury (CoRR, 2024)

Accurate Low-Degree Polynomial Approximation of Non-polynomial Operators for Fast Private Inference in Homomorphic Encryption. - Jianming Tong; Jingtian Dang; Anupam Golder; Callie Hao; Arijit Raychowdhury; Tushar Krishna (CoRR, 2024)

Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Ritik Raj; Chaojian Li; Haoran You; Yonggan Fu; Cheng Wan 005; Sixu Li; Youbin Kim; Ananda Samajdar; Yingyan Celine Lin; et al. (CoRR, 2024)

VAP: The Vulnerability-Adaptive Protection Paradigm Toward Reliable Autonomous Machines. - Zishen Wan; Yiming Gan; Bo Yu 014; Shaoshan Liu; Arijit Raychowdhury; Yuhao Zhu 001 (CoRR, 2024)

E-Gaze: Gaze Estimation With Event Camera. - Nealson Li; Muya Chang; Arijit Raychowdhury (IEEE Trans. Pattern Anal. Mach. Intell., 2024)

A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. - Ashwin Sanjay Lele; Muya Chang; Samuel D. Spetalnick; Brian Crafton; Shota Konno; Zishen Wan; Ashwin Bhat; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2024)

Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs. - Yu-Shun Hsiao; Zishen Wan; Tianyu Jia; Radhika Ghosal; Abdulrahman Mahmoud; Arijit Raychowdhury; David Brooks 001; Gu-Yeon Wei; Vijay Janapa Reddi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Fractionally-Spaced Equalizers as Clock and Data Recovery Loops. - Sigang Ryu; Jaeha Kim; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

The Vulnerability-Adaptive Protection Paradigm. - Zishen Wan; Yiming Gan; Bo Yu 014; Shaoshan Liu; Arijit Raychowdhury; Yuhao Zhu 001 (Commun. ACM, 2024)

ReCA: Integrated Acceleration for Real-Time and Efficient Cooperative Embodied Autonomous Agents. - Zishen Wan; Yuhang Du; Mohamed Ibrahim 002; Jiayi Qian; Jason Jabbour; Yang (Katie) Zhao; Tushar Krishna; Arijit Raychowdhury; Vijay Janapa Reddi (ASPLOS (2), 2025)

CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design. - Zishen Wan; Hanchen Yang; Ritik Raj; Che-Kai Liu; Ananda Samajdar; Arijit Raychowdhury; Tushar Krishna (HPCA, 2025)

A 48V Input Merged Cross-Connected Double Step-Down Converter with Package-Integrated GaN Switches and Silicon Controller IC. - Hua Chen; Young-Seok Noh; Minxiang Gong; Arijit Raychowdhury (ISCAS, 2025)

Optimizing Sparse/Dense VEGETA Accelerator Performance with Microscaling Quantization. - Kazi Barria Nine; Connor Talley; Ajay Sharma Mandadi; Tushar Krishna; Arijit Raychowdhury (ISCAS, 2025)

Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory. - Ying-Hao Wei; Zishen Wan; Brian Crafton; Samuel Spetalnick; Arijit Raychowdhury (ISCAS, 2025)

Generative AI in Embodied Systems: System-Level Analysis of Performance, Efficiency and Scalability. - Zishen Wan; Jiayi Qian; Yuhang Du; Jason Jabbour; Yilun Du; Yang Zhao 013; Arijit Raychowdhury; Tushar Krishna; Vijay Janapa Reddi (ISPASS, 2025)

Efficient Processing of Neuro-Symbolic AI: A Tutorial and Cross-Layer Co-Design Case Study. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Ritik Raj; Arijit Raychowdhury; Tushar Krishna (NeuS, 2025)

FAVbot: An Autonomous Target Tracking Micro-Robot with Frequency Actuation Control. - Zhijian Hao; Ashwin Sanjay Lele; Yan Fang; Arijit Raychowdhury; Azadeh Ansari (CoRR, 2025)

An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2025)

MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-of-Arrival Estimation. - Adou Sangbone Assoa; Ashwin Bhat; Sigang Ryu; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing. - Md Mizanur Rahaman Nayan; Che-Kai Liu; Zishen Wan; Arijit Raychowdhury; Azad J. Naeemi (CoRR, 2025)

NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI. - Hanchen Yang; Zishen Wan; Ritik Raj; Joongun Park; Ziwei Li; Ananda Samajdar; Arijit Raychowdhury; Tushar Krishna (CoRR, 2025)

3DGauCIM: Accelerating Static/Dynamic 3D Gaussian Splatting via Digital CIM for High Frame Rate Real-Time Edge Rendering. - Wei-Hsing Huang; Cheng-Jhih Shih; Jian-Wei Su; Samuel Wade Wang; Vaidehi Garg; Yuyao Kong; Jen-Chun Tien; Nealson Li; Arijit Raychowdhury; Meng-Fan Chang; Yingyan Lin; Shimeng Yu (CoRR, 2025)

Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration. - Shuting Du; Mohamed Ibrahim 002; Zishen Wan; Luqi Zheng; Boheng Zhao; Zhenkun Fan; Che-Kai Liu; Tushar Krishna; Arijit Raychowdhury; Haitong Li (CoRR, 2025)