Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. - Prabir Saha; Arindam Banerjee 003; Partha Bhattacharyya; Anup Dandapat (ISED, 2011)

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. - Prabir Saha; Arindam Banerjee 003; Anup Dandapat; Partha Bhattacharyya (Microelectron. J., 2011)

Design of High Speed Vedic Multiplier for Decimal Number System. - Prabir Saha; Arindam Banerjee 003; Anup Dandapat; Partha Bhattacharyya (VDAT, 2012)

The Design of Reversible Multiplier Using Ancient Indian Mathematics. - Arindam Banerjee 003; Debesh Kumar Das (ISED, 2013)

Squaring in reversible logic using iterative structure. - Arindam Banerjee 003; Debesh Kumar Das (EWDTS, 2014)

Improved matrix multiplier design for high-speed digital signal processing applications. - Prabir Saha; Arindam Banerjee 003; Partha Bhattacharyya; Anup Dandapat (IET Circuits Devices Syst., 2014)

Squarer design with reduced area and delay. - Arindam Banerjee 003; Debesh Kumar Das (VDAT, 2015)

The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics. - Arindam Banerjee 003; Debesh Kumar Das (J. Low Power Electron., 2015)

A new ALU architecture design using reversible logic. - Arindam Banerjee 003; Debesh Kumar Das (ISED, 2016)

Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. - Arindam Banerjee 003; Debesh Kumar Das (VLSID, 2016)

A New Squarer design with reduced area and delay. - Arindam Banerjee 003; Debesh Kumar Das (IET Comput. Digit. Tech., 2016)

Arithmetic Circuits Using Reversible Logic: A Survey Report. - Arindam Banerjee 003; Debesh Kumar Das (ACSS (1), 2019)

A Novel ALU Circuit based on Reversible Logic. - Arindam Banerjee 003; Debesh Kumar Das (J. Circuits Syst. Comput., 2020)