Design and implementation of correlating caches. - Arindam Mallik; Matthew C. Wildrick; Gokhan Memik (ISLPED, 2004)

A Case for Clumsy Packet Processors. - Arindam Mallik; Gokhan Memik (MICRO, 2004)

Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. - Gokhan Memik; Masud H. Chowdhury; Arindam Mallik; Yehea I. Ismail (DSN, 2005)

Load elimination for low-power embedded processors. - Gokhan Memik; Mahmut T. Kandemir; Arindam Mallik (ACM Great Lakes Symposium on VLSI, 2005)

Application-Level Error Measurements for Network Processors. - Arindam Mallik; Matthew C. Wildrick; Gokhan Memik (IEICE Trans. Inf. Syst., 2005)

Low Power Correlating Caches for Network Processors. - Arindam Mallik; Gokhan Memik (J. Low Power Electron., 2005)

Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. - Arindam Mallik; Debjit Sinha; Prithviraj Banerjee; Hai Zhou 001 (DATE, 2006)

User-Driven Frequency Scaling. - Arindam Mallik; Bin Lin 002; Gokhan Memik; Peter A. Dinda; Robert P. Dick (IEEE Comput. Archit. Lett., 2006)

Automated task distribution in multicore network processors using statistical analysis. - Arindam Mallik; Yu Zhang; Gokhan Memik (ANCS, 2007)

The user in experimental computer systems research. - Peter A. Dinda; Gokhan Memik; Robert P. Dick; Bin Lin 002; Arindam Mallik; Ashish Gupta 003; Samuel Rossoff (Experimental Computer Science, 2007)

Variable latency caches for nanoscale processor. - Serkan Ozdemir; Arindam Mallik; Ja Chun Ku; Gokhan Memik; Yehea I. Ismail (SC, 2007)

Power reduction through measurement and modeling of users and CPUs: summary. - Bin Lin 002; Arindam Mallik; Peter A. Dinda; Gokhan Memik; Robert P. Dick (SIGMETRICS, 2007)

Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. - Arindam Mallik; Debjit Sinha; Prithviraj Banerjee; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

PICSEL: measuring user-perceived performance to control dynamic frequency scaling. - Arindam Mallik; Jack Cosgrove; Robert P. Dick; Gokhan Memik; Peter A. Dinda (ASPLOS, 2008)

Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction. - Alex Shye; Berkin Özisikyilmaz; Arindam Mallik; Gokhan Memik; Peter A. Dinda; Robert P. Dick; Alok N. Choudhary (ISCA, 2008)

User- and process-driven dynamic voltage and frequency scaling. - Bin Lin 002; Arindam Mallik; Peter A. Dinda; Gokhan Memik; Robert P. Dick (ISPASS, 2009)

MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs. - Arindam Mallik; Peter Marwedel; Dimitrios Soudris; Sander Stuijk (CASES, 2010)

Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming. - Daniel Cordes; Peter Marwedel; Arindam Mallik (CODES+ISSS, 2010)

A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms. - Yiannis Iosifidis; Arindam Mallik; Stylianos Mamagkakis; Eddy de Greef; Alexandros Bartzas; Dimitrios Soudris; Francky Catthoor (DAC, 2010)

Mapping Embedded Applications on MPSoCs: The MNEMEE Approach. - Christos Baloukas; Lazaros Papadopoulos; Dimitrios Soudris; Sander Stuijk; Olivera Jovanovic; Florian Schmoll; Daniel Cordes; Robert Pyka; Arindam Mallik; Stylianos Mamagkakis; François Capman; Séverin Collet; et al. (ISVLSI, 2010)

Mapping Embedded Applications on MPSoCs: The MNEMEE Approach. - Christos Baloukas; Lazaros Papadopoulos; Dimitrios Soudris; Sander Stuijk; Olivera Jovanovic; Florian Schmoll; Peter Marwedel; Daniel Cordes; Robert Pyka; Arindam Mallik; Stylianos Mamagkakis; François Capman; et al. (ISVLSI (Selected papers), 2010)

Automatic Extraction of Pipeline Parallelism for Embedded Software Using Linear Programming. - Daniel Cordes; Andreas Heinig; Peter Marwedel; Arindam Mallik (ICPADS, 2011)

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. - Arindam Mallik; Paul Zuber; Tsung-Te Liu; Bharani Chava; Bhavana Ballal; Pablo Royer Del Bario; Rogier Baert; Kris Croes; Julien Ryckaert; Mustafa Badaroglu; Abdelkarim Mercha; Diederik Verkest (DAC, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Lateral NWFET optimization for beyond 7nm nodes. - Dmitry Yakimets; Doyoung Jang; Praveen Raghavan; Geert Eneman; Hans Mertens; P. Schuddinck; Arindam Mallik; Marie Garcia Bardon; Nadine Collaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; et al. (ICICDT, 2015)

Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling. - A. Vandooren; Liesbeth Witters; Jacopo Franco; Arindam Mallik; Bertrand Parvais; Z. Wu; Amey Walke; V. Deshpande; E. Rosseel; Andriy Hikavyy; W. Li; L. Peng; et al. (ICICDT, 2018)

FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. - Bram-Ernst Verhoef; Nathan Laubeuf; Stefan Cosemans; Peter Debacker; Ioannis A. Papistas; Arindam Mallik; Diederik Verkest (CoRR, 2019)

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. - Ioannis A. Papistas; Stefan Cosemans; Bram Rooseleer; Jonas Doevenspeck; Myung Hee Na; Arindam Mallik; Peter Debacker; Diederik Verkest (CICC, 2021)

Noise tolerant ternary weight deep neural networks for analog in-memory inference. - Jonas Doevenspeck; Peter Vrancx; Nathan Laubeuf; Arindam Mallik; Peter Debacker; Diederik Verkest; Rudy Lauwereins; Wim Dehaene (IJCNN, 2021)

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. - Debjyoti Bhattacharjee; Nathan Laubeuf; Stefan Cosemans; Ioannis A. Papistas; Arindam Mallik; Peter Debacker; Myung Hee Na; Diederik Verkest (ISCAS, 2021)

Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. - Michele Caselli; Ioannis A. Papistas; Stefan Cosemans; Arindam Mallik; Peter Debacker; Diederik Verkest (NEWCAS, 2021)

Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications. - Daisuke Saito; Toshiyuki Kobayashi; Hiroki Koga; Nicolo Ronchi; Kaustuv Banerjee; Yusuke Shuto; Jun Okuno; Kenta Konishi; Luca Di Piazza; Arindam Mallik; Jan Van Houdt; Masanori Tsukamoto; et al. (VLSI Circuits, 2021)

Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation. - Michele Caselli; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest (ISCAS, 2022)

Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing. - Michele Caselli; Subhali Subhechha; Peter Debacker; Arindam Mallik; Diederik Verkest (ISCAS, 2022)

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. - Kodai Ueyoshi; Ioannis A. Papistas; Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Man Shi; Qilin Zheng; Juan Sebastian Piedrahita Giraldo; Peter Vrancx; Jonas Doevenspeck; Debjyoti Bhattacharjee; Stefan Cosemans; et al. (ISSCC, 2022)

AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators. - Simei Yang; Debjyoti Bhattacharjee; Vinay B. Y. Kumar; Saikat Chatterjee; Sayandip De; Peter Debacker; Diederik Verkest; Arindam Mallik; Francky Catthoor (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. - Nathan Laubeuf; Jonas Doevenspeck; Ioannis A. Papistas; Michele Caselli; Stefan Cosemans; Peter Vrancx; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Francky Catthoor; Rudy Lauwereins (ACM Trans. Design Autom. Electr. Syst., 2022)

Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator. - Swatilekha Majumdar; Stefan Cosemans; Arindam Mallik; Peter Debacker; Francky Catthoor; Jan Van Houdt (ISCAS, 2023)

AIMC Modeling and Parameter Tuning for Layer-Wise Optimal Operating Point in DNN Inference. - Iman Dadras; Giuseppe Maria Sarda; Nathan Laubeuf; Debjyoti Bhattacharjee; Arindam Mallik (IEEE Access, 2023)

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. - Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Kodai Ueyoshi; Ioannis A. Papistas; Man Shi; Qilin Zheng; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Marian Verhelst (IEEE J. Solid State Circuits, 2023)

Performance Modeling and Workload Analysis of Distributed Large Language Model Training and Inference. - Joyjit Kundu; Wenzhe Guo; Ali BanaGozar; Udari De Alwis; Sourav Sengupta 001; Puneet Gupta; Arindam Mallik (IISWC, 2024)

Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems. - Aakash Patel; Dwaipayan Biswas; Joyjit Kundu; Yoojin Ban; Nicolas Pantano; Arindam Mallik; Julien Ryckaert; James Myers (ISVLSI, 2024)

SAfEPaTh: A System-Level Approach for Efficient Power and Thermal Estimation of Convolutional Neural Network Accelerator. - Yukai Chen; Simei Yang; Debjyoti Bhattacharjee; Francky Catthoor; Arindam Mallik (CoRR, 2024)

On-the-fly Validation of Hierarchical Cache Coherence Protocols using Directed Testing. - Abhinaba Chakraborty; Ansuman Banerjee; Vinay B. Y. Kumar; Arindam Mallik (ISVLSI, 2025)