A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC. - Samiran Halder; Swapna Banerjee; Arindrajit Ghosh; Ravi Sankar Prasad; Anirban Chatterjee; Sanjoy Kumar Dey (VLSI Design, 2005)

A 160MSPS 8-Bit Pipeline Based ADC. - Samiran Halder; Arindrajit Ghosh; Ravi Sankar Prasad; Anirban Chatterjee; Swapna Banerjee (VLSI Design, 2005)

A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. - Santanu Sarkar 002; Arindrajit Ghosh; Swapna Banerjee (APCCAS, 2006)

Contention free delayed keeper for high density large signal sensing memory compiler. - Arindrajit Ghosh; Uddalak Bhattacharya; Swapna Banerjee (Integr., 2018)

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology. - Arindrajit Ghosh; Uddalak Bhattacharya; Manish Kumar; Swapna Banerjee (Integr., 2020)