Pipelined Memory Shared Buffer for VLSI Switches. - Manolis Katevenis; Panagiota Vatsolaki; Aristides Efthymiou (SIGCOMM, 1995)

Power Management in the Amulet Microprocessors. - Stephen B. Furber; Aristides Efthymiou; Jim D. Garside; David W. Lloyd; Mike J. G. Lewis; Steve Temple (IEEE Des. Test Comput., 2001)

Adaptive Pipeline Depth Control for Processor Power-Management. - Aristides Efthymiou; Jim D. Garside (ICCD, 2002)

An adaptive serial-parallel CAM architecture for low-power cache blocks. - Aristides Efthymiou; Jim D. Garside (ISLPED, 2002)

Adaptive Pipeline Structures fo Speculation Control. - Aristides Efthymiou; Jim D. Garside (ASYNC, 2003)

An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. - Aristides Efthymiou; W. Suntiamorntut; Jim D. Garside; L. E. M. Brackenbury (ASYNC, 2004)

Adding Testability to an Asynchronous Interconnect for GALS SoC. - Aristides Efthymiou; John Bainbridge; Douglas A. Edwards (Asian Test Symposium, 2004)

Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. - Aristides Efthymiou; Christos P. Sotiriou; Douglas A. Edwards (DATE, 2004)

A CAM with mixed serial-parallel comparison for use in low energy caches. - Aristides Efthymiou; Jim D. Garside (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A Low-Power Processor Architecture Optimized forWireless Devices. - Aristides Efthymiou; Jim D. Garside; Ioannis Papaefstathiou (ASAP, 2005)

Fast, Parallel Two-Rail Code Checker with Enhanced Testability. - Sotirios Matakias; Y. Tsiatouhas; Themistoklis Haniotakis; Angela Arapoyanni; Aristides Efthymiou (IOLTS, 2005)

Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. - Aristides Efthymiou; John Bainbridge; Douglas A. Edwards (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Synthetic Trace-Driven Simulation of Cache Memory. - Rahman Hassan; Antony Harris; Nigel P. Topham; Aristides Efthymiou (AINA Workshops (1), 2007)

Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. - Aristides Efthymiou (DDECS, 2007)

A Partial Scan Based Test Generation for Asynchronous Circuits. - Dilip P. Vasudevan; Aristides Efthymiou (DDECS, 2008)

Optimising Self-Timed FPGA Circuits. - Phillip David Ferguson; Aristides Efthymiou; Tughrul Arslan; Danny Hume (DSD, 2010)

Initialization-Based Test Pattern Generation for Asynchronous Circuits. - Aristides Efthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2010)

An error tolerant CAM with nand match-line organization. - Aristides Efthymiou (ACM Great Lakes Symposium on VLSI, 2013)

An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems. - Marina E. Plissiti; Christoforos Papaioannou; Yiorgos Sfikas; Georgios Papatheodorou; Simon-Ilias Poulis; Aristides Efthymiou; Yiorgos Tsiatouhas (MeditCom, 2021)

Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles. - Christoforos Papaioannou; Marina E. Plissiti; Yiorgos Sfikas; Georgios Papatheodorou; Simon-Ilias Poulis; Aristides Efthymiou; Yiorgos Tsiatouhas (BlackSeaCom, 2022)

Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems. - Marina E. Plissiti; Christoforos Papaioannou; Yiorgos Sfikas; Georgios Papatheodorou; Simon-Ilias Poulis; Aristides Efthymiou; Yiorgos Tsiatouhas (ICAIIC, 2024)

Exploring the Design Space of 32x32 Approximate Reduced Complexity Wallace Multipliers. - Ioannis Rizos; Georgios Papatheodorou; Aristides Efthymiou (MOCAST, 2024)

Tunable Approximate Booth Multiplier. - Ioannis Rizos; Georgios Papatheodorou; Aristides Efthymiou (ISVLSI, 2025)