An Efficient Finite Element Method for Submicron IC Capacitance Extraction. - N. P. van der Meijs; Arjan J. van Genderen (DAC, 1989)

Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures. - Arjan J. van Genderen; N. P. van der Meijs (ICCAD, 1993)

Delayed Frontal Solution for Finite-Element Based Resistance Extraction. - N. P. van der Meijs; Arjan J. van Genderen (DAC, 1995)

Network initialization in a switch-level simulator. - Arjan J. van Genderen (ED&TC, 1995)

Extraction of circuit models for substrate cross-talk. - T. Smedes; N. P. van der Meijs; Arjan J. van Genderen (ICCAD, 1995)

Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. - Frederik Beeftink; Arjan J. van Genderen; N. P. van der Meijs (ICCD, 1995)

Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction. - Arjan J. van Genderen; N. P. van der Meijs (DAC, 1996)

Fast Computation of Substrate Resistances in Large Circuits. - Arjan J. van Genderen; N. P. van der Meijs; T. Smedes (ED&TC, 1996)

Can SG-FET Replace FET in Sleep Mode Circuits? - Marius Enachescu; Sorin Cotofana; Arjan J. van Genderen; Dimitrios Tsamados; Adrian M. Ionescu (NanoNet, 2009)