A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit. - Arjun Ramaswami Palaniappan; Dominic Maurath; Felix Kalathiparambil; Liter Siek (ISCAS, 2015)

Review of pulse generators for gated ring oscillator based Time-to-Digital converters. - Jian Sen Teh; Arjun Ramaswami Palaniappan; Liter Siek; Yuanjin Zheng (ISIC, 2016)

A 0.0186 mm2, 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants. - Arjun Ramaswami Palaniappan; Liter Siek (NORCAS, 2018)

A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS. - Arjun Ramaswami Palaniappan; Liter Siek (ISCAS, 2019)

A TDC-less all-digital phase locked loop for medical implant applications. - Arjun Ramaswami Palaniappan; Liter Siek (Microprocess. Microsystems, 2019)