Novel Randomized & Biased Placement for FPGA Based Robust Random Number Generator with Enhanced Uniqueness. - Arjun Singh Chauhan; Vineet Sahula; Atanendu S. Mandal (VLSID, 2019)

Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness. - Arjun Singh Chauhan; Vineet Sahula; Atanendu Sekhar Mandal (J. Electron. Test., 2019)

Correction to: Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness. - Arjun Singh Chauhan; Vineet Sahula; Atanendu Sekhar Mandal (J. Electron. Test., 2019)

Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number Generation. - Arjun Singh Chauhan; Vineet Sahula; A. S. Mandal; Abhigyan Dutta (VLSID, 2020)

An Automatic Pitch Deck Analyzer. - Arjun Singh Chauhan; Ashu Sharma; Himanshi Bhatia (COMAD/CODS (December), 2024)