Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization. - Arkadiy Morgenshtein; Alexander Fish; Israel A. Wagner (ISCAS (1), 2002)

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. - Arkadiy Morgenshtein; Alexander Fish; Israel A. Wagner (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. - Arkadiy Morgenshtein; Michael Moreinis; Israel A. Wagner; Avinoam Kolodny (VLSI-SOC, 2003)

Automatic hardware-efficient SoC integration by QoS network on chip. - Evgeny Bolotin; Arkadiy Morgenshtein; Israel Cidon; Ran Ginosar; Avinoam Kolodny (ICECS, 2004)

Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization. - Michael Moreinis; Arkadiy Morgenshtein; Israel A. Wagner; Avinoam Kolodny (ICECS, 2004)

Micro-modem - reliability solution for NoC communications. - Arkadiy Morgenshtein; Evgeny Bolotin; Israel Cidon; Avinoam Kolodny; Ran Ginosar (ICECS, 2004)

ISFET CMOS compatible design and encapsulation challenges. - Liby Sudakov-Boreysha; Arkadiy Morgenshtein; Uri Dinnar; Yael Nemirovsky (ICECS, 2004)

An efficient implementation of D-Flip-Flop using the GDI technique. - Arkadiy Morgenshtein; Alexander Fish; Israel A. Wagner (ISCAS (2), 2004)

Comparative analysis of serial vs parallel links in NoC. - Arkadiy Morgenshtein; Israel Cidon; Avinoam Kolodny; Ran Ginosar (SoC, 2004)

Asynchronous gate-diffusion-input (GDI) circuits. - Arkadiy Morgenshtein; Michael Moreinis; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Low-leakage repeaters for NoC interconnects. - Arkadiy Morgenshtein; Israel Cidon; Ran Ginosar; Avinoam Kolodny (ISCAS (1), 2005)

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. - Michael Moreinis; Arkadiy Morgenshtein; Israel A. Wagner; Avinoam Kolodny (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Parallel vs. serial on-chip communication. - Rostislav (Reuven) Dobkin; Arkadiy Morgenshtein; Avinoam Kolodny; Ran Ginosar (SLIP, 2008)

Timing optimization in logic with interconnect. - Arkadiy Morgenshtein; Eby G. Friedman; Ran Ginosar; Avinoam Kolodny (SLIP, 2008)

Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. - Arkadiy Morgenshtein; Eby G. Friedman; Ran Ginosar; Avinoam Kolodny (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. - Arkadiy Morgenshtein; Eby G. Friedman; Ran Ginosar; Avinoam Kolodny (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Effective post-silicon failure localization using dynamic program slicing. - Ophir Friedler; Wisam Kadry; Arkadiy Morgenshtein; Amir Nahir; Vitali Sokhin (DATE, 2014)

Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design. - Arkadiy Morgenshtein; Viacheslav Yuzhaninov; Alexey Kovshilovsky; Alexander Fish (Integr., 2014)

Comparative study of test generation methods for simulation accelerators. - Wisam Kadry; Dmitry Krestyashyn; Arkadiy Morgenshtein; Amir Nahir; Vitali Sokhin; Jin Sung Park; Sung-Boem Park; Wookyeong Jeong; Jae-Cheol Son (DATE, 2015)

Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. - Doowon Lee; Tom Kolan; Arkadiy Morgenshtein; Vitali Sokhin; Ronny Morad; Avi Ziv; Valeria Bertacco (DAC, 2016)

Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms. - Wisam Kadry; Dmitry Krestyashyn; Arkadiy Morgenshtein; Amir Nahir; Vitali Sokhin; Jin Sung Park; Sung-Boem Park; Wookyeong Jeong; Jae-Cheol Son (IEEE Des. Test, 2017)