A 1.5-V supply, video range frequency, Gm-C filter. - Armin Tajalli; Mojtaba Atarodi; Akbar Adibi (ISCAS, 2000)

A low-power subscriber line interface circuit in a high-voltage CMOS technology. - Mohammad B. Vahidfar; Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS (5), 2002)

A compact, low power, fully integrated clock frequency doubler. - Armin Tajalli; Abbas Khodaverdi; Seyed Mojtaba Atarodi (ICECS, 2003)

A compact biquadratic gm-C filter structure for low-voltage and high frequency applications. - Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS (1), 2003)

Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology. - Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS (1), 2003)

Structured design of an integrated subscriber line interface system and circuit. - Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS (2), 2003)

Design and optimization of a high PSRR CMOS bandgap voltage reference. - Armin Tajalli; Seyed Mojtaba Atarodi; Abbas Khodaverdi; Farzad Sahandi Esfanjani (ISCAS (1), 2004)

A duty cycle control circuit for high speed applications. - Armin Tajalli; Saeid Mehrmanesh; Seyed Mojtaba Atarodi (ISCAS (1), 2004)

A fractional delay-locked loop for on chip clock generation applications. - Pooya Torkzadeh; Armin Tajalli; Seyed Mojtaba Atarodi (ASP-DAC, 2005)

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. - Paul Muller; Armin Tajalli; Seyed Mojtaba Atarodi; Yusuf Leblebici (DATE, 2005)

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology. - Armin Tajalli; Paul Muller; Mojtaba Atarodi; Yusuf Leblebici (ESSCIRC, 2005)

Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops. - Pooya Torkzadeh; Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS (3), 2005)

A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer. - Pooya Torkzadeh; Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS (5), 2005)

A low-power, multichannel gated oscillator-based CDR for short-haul applications. - Armin Tajalli; Paul Muller; Seyed Mojtaba Atarodi; Yusuf Leblebici (ISLPED, 2005)

A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications. - Mohsen Moezzi; Ramin Zanbaghi; Mojtaba Atarodi; Armin Tajalli (ICECS, 2006)

A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system. - Habib Adrang; Reza Lotfi; Khalil Mafinejhad; Armin Tajalli; Saeed Mehrmanesh (ISCAS, 2006)

A technique to suppress tail current flicker noise in CMOS LC VCOs. - Saeed Saeedi; Saeid Mehrmanesh; Armin Tajalli; Seyed Mojtaba Atarodi (ISCAS, 2006)

A 1/4 rate linear phase detector for PLL-based CDR circuits. - Mohsen Saffari; Seyed Mojtaba Atarodi; Armin Tajalli (ISCAS, 2006)

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. - Armin Tajalli; Paul Muller; Seyed Mojtaba Atarodi; Yusuf Leblebici (ISCAS, 2006)

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. - Armin Tajalli; Eric A. Vittoz; Yusuf Leblebici; Elizabeth J. Brauer (ESSCIRC, 2007)

A Power Optimized Base-Band Circuitry for the Low-IF Receivers. - Ramin Zanbaghi; Seyed Mojtaba Atarodi; Armin Tajalli (ISCAS, 2007)

Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits. - Armin Tajalli; Paul Muller; Yusuf Leblebici (J. Low Power Electron., 2007)

A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. - Armin Tajalli; Paul Muller; Yusuf Leblebici (IEEE J. Solid State Circuits, 2007)

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology. - Thomas Liechti; Armin Tajalli; Omer Can Akgun; Zeynep Toprak Deniz; Yusuf Leblebici (APCCAS, 2008)

Improving the power-delay product in SCL circuits using source follower output stage. - Armin Tajalli; Frank K. Gürkaynak; Yusuf Leblebici; Massimo Alioto; Elizabeth J. Brauer (ISCAS, 2008)

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. - Armin Tajalli; Massimo Alioto; Elizabeth J. Brauer; Yusuf Leblebici (PATMOS, 2008)

Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance. - Pooyan Sakian; Mohsen Saffari; Seyed Mojtaba Atarodi; Armin Tajalli (IET Circuits Devices Syst., 2008)

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. - Armin Tajalli; Elizabeth J. Brauer; Yusuf Leblebici; Eric A. Vittoz (IEEE J. Solid State Circuits, 2008)

A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold. - Armin Tajalli; Yusuf Leblebici (CICC, 2009)

Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems. - Armin Tajalli; Yusuf Leblebici (ESSCIRC, 2009)

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. - Armin Tajalli; Yusuf Leblebici (ISCAS, 2009)

A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. - Armin Tajalli; Yusuf Leblebici (IEEE J. Solid State Circuits, 2009)

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. - Armin Tajalli; Elizabeth J. Brauer; Yusuf Leblebici (Microelectron. J., 2009)

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. - Armin Tajalli; Massimo Alioto; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Leakage Current Reduction Using Subthreshold Source-Coupled Logic. - Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. - Armin Tajalli; Yusuf Leblebici (DATE, 2010)

Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. - Armin Tajalli; Yusuf Leblebici (ESSCIRC, 2010)

A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems. - Armin Tajalli; Yusuf Leblebici (ESSCIRC, 2010)

Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. - Armin Tajalli; Yusuf Leblebici (J. Low Power Electron., 2010)

Design trade-offs in ultra-low-power CMOS and STSCL digital systems. - Armin Tajalli; Yusuf Leblebici (ECCTD, 2011)

Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. - Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. - Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL. - Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces. - Nikola Katic; Ibrahim Kazi; Armin Tajalli; Alexandre Schmid; Yusuf Leblebici (NORCHIP, 2014)

Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. - Mahsa Shoaran; Armin Tajalli; Massimo Alioto; Yusuf Leblebici (ISCAS, 2015)

10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (ISSCC, 2015)

A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (VLSIC, 2015)

A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces. - Nikola Katic; Ibrahim Kazi; Armin Tajalli; Alexandre Schmid; Yusuf Leblebici (Int. J. Circuit Theory Appl., 2015)

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE J. Solid State Circuits, 2015)

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. - Mahsa Shoaran; Armin Tajalli; Massimo Alioto; Alexandre Schmid; Yusuf Leblebici (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. - Kiarash Gharibdoust; Gain Kim; Armin Tajalli; Yusuf Leblebici (ISCAS, 2016)

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS. - Amin Shokrollahi; Dario Albino Carnelli; John Fox; Klaas L. Hofstra; Brian Holden; Ali Hormati; Peter Hunt; Margaret Johnston; John Keay; Sergio Pesenti; Richard Simpson 004; David Stauffer; et al. (ISSCC, 2016)

A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (NEWCAS, 2016)

A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE J. Solid State Circuits, 2016)

A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. - Gain Kim; Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. - Gain Kim; Chen Cao; Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. - Ayca Akkaya; Firat Celik; Armin Tajalli; Yusuf Leblebici (NORCAS, 2018)

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics. - Farzan Jazaeri; Arnout Beckers; Armin Tajalli; Jean-Michel Sallese (MIXDES, 2019)

Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology. - Jacob Atkinson; Amin Aghighi; Stuart Anderson; Anthony Bailey; Mitchell Crane; Armin Tajalli (MWSCAS, 2019)

Spectrum-Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling. - Rajath Bindiganavile; Armin Tajalli (MWSCAS, 2019)

CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology. - Amin Aghighi; Jacob Atkinson; Nickolas Bybee; Stuart Anderson; Mitchell Crane; Anthony Bailey; Reuben Morell; Ahmed Hassanin; Armin Tajalli (NEWCAS, 2019)

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. - Firat Celik; Ayca Akkaya; Armin Tajalli; Yusuf Leblebici (NEWCAS, 2019)

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. - Firat Celik; Ayca Akkaya; Armin Tajalli; Andreas Burg 001; Yusuf Leblebici (PRIME, 2019)

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; John Fox; Kiarash Gharibdoust; Davide Gorret; Amit Gupta; Christopher Hall; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; et al. (VLSI Circuits, 2019)

Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; Kiarash Gharibdoust; Amit Gupta; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; Ali Hormati; John Keay; Amin Shokrollahi; et al. (CICC, 2020)

Power System Emulator Based on PLL Architecture. - Asif Wahid; Sayed Abdullah Sadat; Mostafa Ardakani; Armin Tajalli (ISCAS, 2020)

Digitally-Assisted Peak Detector for Periodic Signal. - Asif Wahid; Armin Tajalli (MWSCAS, 2020)

Energy and Area Efficient Mixed-Mode MCMC MIMO Detector. - Amin Aghighi; Behrouz Farhang-Boroujeny; Armin Tajalli (VLSI-SOC, 2020)

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector. - Amin Aghighi; Behrouz Farhang-Boroujeny; Armin Tajalli (VLSI-SoC (Selected Papers), 2020)

An ULP Self-Supplied Brain Interface Circuit. - Amin Aghighi; Massood Tabib-Azar; Armin Tajalli (VLSI-SOC, 2020)

A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. - Amin Aghighi; Armin Tajalli; Mohammad Taherzadeh-Sani (VLSI-SOC, 2020)

A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET. - Armin Tajalli; Mani Bastani Parizi; Dario Albino Carnelli; Chen Cao; Kiarash Gharibdoust; Davide Gorret; Amit Gupta; Christopher Hall; Ahmed Hassanin; Klaas L. Hofstra; Brian Holden; Ali Hormati; et al. (IEEE J. Solid State Circuits, 2020)

Optimal PAM Order for Wireline Communication. - Asif Wahid; Rajath Bindiganavile; Armin Tajalli (ISCAS, 2021)

A Controllable KVCO Ring VCO Topology. - Rajath Bindiganavile; Armin Tajalli (MWSCAS, 2021)

Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology. - Armin Tajalli (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. - Firat Celik; Ayca Akkaya; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Balanced Circuit Topologies and Their Applications in Data Movement. - Armin Tajalli; Amin Shokrollahi (MWSCAS, 2022)

Systematic Design of Loop Circuit Topologies Using C/IDS Methodology. - Jacob Atkinson; Anthony Bailey; Armin Tajalli (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization. - Shea Smith; Taylor Barton; Yen-Cheng Kuan; Armin Tajalli; Mau-Chung Frank Chang; Shiuh-Hua Wood Chiang (A-SSCC, 2023)

Computational Efficiency of Circuit Design and Optimization Algorithms: A Comparative Study. - Alec Adair; Armin Tajalli (ISCAS, 2023)

A VCO Linearization Technique Using Dual-VCO and Interpolation for Time-Based ADCs. - Shea Smith; Armin Tajalli; Shiuh-Hua Wood Chiang (MWSCAS, 2023)

Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology. - Behdad Jamadi; Fariborz T. Ordubadi; Armin Tajalli (SMACD, 2023)

Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers. - Sakthidasan Kalidasan; Armin Tajalli (SMACD, 2023)

Noise-Aware FET Circuit Design Based on C/ID-Invariant. - Asif Wahid; Jacob Atkinson; Rajath Bindiganavile; Farzan Jazaeri; Armin Tajalli (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI. - Rajath Bindiganavile; Asif Wahid; Armin Tajalli (CICC, 2024)

Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication. - Asif Wahid; Rajath Bindiganavile; Armin Tajalli (ISCAS, 2024)

Speed-Noise-Power Trade-Offs in Design of Scaled FET Circuits Using $ mathrm{C}/ mathrm{I}_{ mathrm{D}}$ Methodology. - Armin Tajalli (LASCAS, 2024)

Effect of Parameter Drift on the Accuracy of Analog CNN Accelerators. - Michael Keyser; Farzad T. Ordubadi; Armin Tajalli (MWSCAS, 2024)

Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers. - Behdad Jamadi; Shiuh-Hua Wood Chiang; Armin Tajalli (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Digital Background Calibration Circuit for Coarse-Fine Timing Mismatch in VCO-Based ADCs. - Shea Smith; Armin Tajalli; Yen-Cheng Kuan; Shiuh-Hua Wood Chiang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling. - Armin Tajalli; Cosimo Aprile; Milad Ataei; Rolf Beerwerth; Dario Carneli; Maik Fuhs; Kiarash Gharibdoust; Ali Hormati; James Hudner; Victor Perrin; Amin Shokrollahi; Richard Simpson 004; et al. (CICC, 2025)