Imprecise security: quality and complexity tradeoffs for hardware information flow tracking. - Wei Hu 008; Andrew Becker; Armita Ardeshiricham; Yu Tai; Paolo Ienne; Dejun Mu; Ryan Kastner (ICCAD, 2016)

Towards Property Driven Hardware Security. - Wei Hu 008; Alric Althoff; Armita Ardeshiricham; Ryan Kastner (MTV, 2016)

Register transfer level information flow tracking for provably secure hardware design. - Armaiti Ardeshiricham; Wei Hu 008; Joshua Marxen; Ryan Kastner (DATE, 2017)

Clepsydra: Modeling timing flows in hardware designs. - Armaiti Ardeshiricham; Wei Hu 008; Ryan Kastner (ICCAD, 2017)

Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans. - Wei Hu 008; Lu Zhang; Armaiti Ardeshiricham; Jeremy Blackstone; Bochuan Hou; Yu Tai; Ryan Kastner (ICCAD, 2017)

Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities. - Wei Hu 008; Armaiti Ardeshiricham; Ryan Kastner (MTV, 2017)

Examining the consequences of high-level synthesis optimizations on power side-channel. - Lu Zhang; Wei Hu 008; Armaiti Ardeshiricham; Yu Tai; Jeremy Blackstone; Dejun Mu; Ryan Kastner (DATE, 2018)

Property specific information flow analysis for hardware security verification. - Wei Hu 008; Armaiti Ardeshiricham; Mustafa S. Gobulukoglu; Xinmu Wang; Ryan Kastner (ICCAD, 2018)

VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties. - Armaiti Ardeshiricham; Yoshiki Takashima; Sicun Gao; Ryan Kastner (CCS, 2019)

A Unified Model for Gate Level Propagation Analysis. - Jeremy Blackstone; Wei Hu 008; Alric Althoff; Armaiti Ardeshiricham; Lu Zhang; Ryan Kastner (CoRR, 2020)

Integrating Information Flow Tracking into High-Level Synthesis Design Flow. - Wei Hu 008; Armaiti Ardeshiricham; Lingjuan Wu; Ryan Kastner (Behavioral Synthesis for Hardware Security, 2022)

Hardware Information Flow Tracking. - Wei Hu 008; Armaiti Ardeshiricham; Ryan Kastner (ACM Comput. Surv., 2022)