3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. - Arnaud Poittevin; Chhandak Mukherjee; Ian O'Connor; Cristell Maneux; Guilhem Larrieu; Marina Deng; Sébastien Le Beux; François Marc; Aurélie Lecestre; Cédric Marchand 002; Abhishek Kumar (VLSI-SoC (Selected Papers), 2020)

3D logic cells design and results based on Vertical NWFET technology including tied compact model. - C. Mukherjee 001; Marina Deng; François Marc; Cristell Maneux; Arnaud Poittevin; Ian O'Connor; Sébastien Le Beux; Abhishek Kumar; Aurélie Lecestre; Guilhem Larrieu (CoRR, 2020)

Emerging Technologies: Challenges and Opportunities for Logic Synthesis. - Alberto Bosio; Mayeul Cantan; Cédric Marchand 002; Ian O'Connor; Petr Fiser; Arnaud Poittevin; Marcello Traiola (DDECS, 2021)

A Logic Cell Design and routing Methodology Specific to VNWFET. - Arnaud Poittevin; Ian O'Connor; Cédric Marchand 002; Alberto Bosio; Cristell Maneux; Chhandak Mukherjee; Guilhem Larrieu; Abhishek Kumar (NEWCAS, 2022)

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. - Lucas Réveil; Chhandak Mukherjee; Cristell Maneux; Marina Deng; François Marc; Abhishek Kumar; Aurélie Lecestre; Guilhem Larrieu; Arnaud Poittevin; Ian O'Connor; Oskar Baumgartner; David Pirker (VLSI-SoC, 2022)