MM11 based flash memory cell model including characterization procedure. - B. Saillet; Arnaud Régnier; Jean-Michel Portal; B. Delsuc; Romain Laffont; Pascal Masson; Rachid Bouchakour (ISCAS, 2006)

Dynamic stress method for accurate NVM oxide robustness evaluation for automotive applications. - D. Pic; Arnaud Régnier; V. Pean; Jean-Luc Ogier; Didier Goguenheim (Microelectron. Reliab., 2008)

Leakage paths identification in NVM using biased data retention. - Jérémy Postel-Pellerin; Romain Laffont; Gilles Micolau; Frédéric Lalande; Arnaud Régnier; Bernard Bouteille (Microelectron. Reliab., 2010)

Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability. - Guillaume Just; Vincenzo Della Marca; Arnaud Régnier; Jean-Luc Ogier; Jérémy Postel-Pellerin; Jean-Michel Portal; Pascal Masson (J. Low Power Electron., 2012)

Effects of 1064 nm laser on MOS capacitor. - R. Llido; Pascal Masson; Arnaud Régnier; Vincent Goubier; Gérald Haller; Vincent Pouget; Dean Lewis (Microelectron. Reliab., 2012)

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology. - Jordan Innocenti; Loic Welter; Franck Julien; Laurent Lopez; Jacques Sonzogni; Stephan Niel; Arnaud Régnier; Emmanuel Paire; Karen Labory; Eric Denis; Jean-Michel Portal; Pascal Masson (MWSCAS, 2014)

Layout optimizations to decrease internal power and area in digital CMOS standard cells. - Jordan Innocenti; Franck Julien; Jean-Michel Portal; Laurent Lopez; Q. Hubert; Pascal Masson; Jacques Sonzogni; Stephan Niel; Arnaud Régnier (MIPRO, 2015)

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip. - Thibault Kempf; Vincenzo Della Marca; L. Baron; F. Maugain; Francesco La Rosa; Stephan Niel; Arnaud Régnier; Jean-Michel Portal; Pascal Masson (IRPS, 2018)

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction. - Vincenzo Della Marca; Jérémy Postel-Pellerin; Thibault Kempf; Arnaud Régnier; Philippe Chiquet; Marc Bocquet (Microelectron. Reliab., 2018)

AC stress reliability study of a new high voltage transistor for logic memory circuits. - Jordan Locati; Vincenzo Della Marca; Christian Rivero; Arnaud Régnier; Stephan Niel; Karine Coulié (IRPS, 2020)

Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology. - Paul Devoge; Hassen Aziza; Philippe Lorenzini; Franck Julien; Abderrezak Marzaki; Alexandre Malherbe; Marc Mantelli; Thomas Sardin; Sébastien Haendler; Arnaud Régnier; Stephan Niel (DTIS, 2021)

Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology. - Romeric Gay; Vincenzo Della Marca; Hassen Aziza; Arnaud Régnier; Stephan Niel; Abderrezak Marzaki (DTIS, 2021)

Simulation of state of the art EEPROM programming window closure during endurance degradation. - Franck Matteo; Roberto Simola; Franck Melul; Karine Coulié; Jérémy Postel-Pellerin; Arnaud Régnier (DTIS, 2021)

Hot Electron Source Side Injection Comprehension in 40nm eSTM™. - Franck Melul; Thibault Kempf; Vincenzo Della Marca; Marc Bocquet; Madjid Akbal; Frederique Trenteseaux; Marc Mantelli; Arnaud Régnier; Stephan Niel; Francesco La Rosa (IMW, 2021)

A Schmitt trigger to benchmark the performance of a new zero-cost transistor. - Paul Devoge; Hassen Aziza; Philippe Lorenzini; Pascal Masson; Alexandre Malherbe; Franck Julien; Abderrezak Marzaki; Arnaud Régnier; Stephan Niel (ICECS 2022, 2022)

Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor. - Paul Devoge; Hassen Aziza; Philippe Lorenzini; Alexandre Malherbe; Franck Julien; Abderrezak Marzaki; Arnaud Régnier; Stephan Niel (ISCAS, 2022)

Notched gate MOSFET for capacitance reduction in RF SOI technology. - Lucas Antunes Tambara; Pascal Masson; Julien Amouroux; Stéphane Monfray; Julien Dura; Frederic Gianesello; Julien Babic; Romain Debroucke; Loic Welter; Siddhartha Dhar; Bernadette Gros; Clement Charbuillet; et al. (DTTIS, 2023)

40nm SONOS Embedded Select in Trench Memory. - Radouane Habhab; Vincenzo Della Marca; Pascal Masson; Nadia Miridi; Clement Pribat; Simon Jeannot; Thibault Kempf; Marc Mantelli; Philippe Lorenzini; Jean-Marc Voisin; Arnaud Régnier; Stephan Niel; et al. (ESSDERC, 2023)