Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA. - Tobias Wiersema; Arne Bockhorn; Marco Platzner (ReConFig, 2014)

An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip. - Tobias Wiersema; Arne Bockhorn; Marco Platzner (Comput. Electr. Eng., 2016)

Checkpointing Approaches for the Computation of Adjoints Covering Resilience Issues. - Arne Bockhorn; Sri Hari Krishna Narayanan; Andrea Walther (CSC, 2020)

Timing Optimization for Virtual FPGA Configurations. - Linus Witschen; Tobias Wiersema; Masood Raeisi Nafchi; Arne Bockhorn; Marco Platzner (ARC, 2021)