Memory in processor: a novel design paradigm for supercomputing architectures. - Nagarajan Venkateswaran; Aditya Krishnan 002; S. Niranjan Kumar; Arrvindh Shriraman; Srinivas Sridharan (SIGARCH Comput. Archit. News, 2004)

Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance. - Nagarajan Venkateswaran; Arrvindh Shriraman; Niranjan Soundararajan (IPDPS, 2005)

PASCOM: Power Model for Supercomputers. - Arrvindh Shriraman; Nagarajan Venkateswaran; Niranjan Soundararajan (ARCS, 2006)

An integrated hardware-software approach to flexible transactional memory. - Arrvindh Shriraman; Michael F. Spear; Hemayet Hossain; Virendra J. Marathe; Sandhya Dwarkadas; Michael L. Scott (ISCA, 2007)

Alert-on-update: a communication aid for shared memory multiprocessors. - Michael F. Spear; Arrvindh Shriraman; Hemayet Hossain; Sandhya Dwarkadas; Michael L. Scott (PPoPP, 2007)

Nonblocking transactions without indirection using alert-on-update. - Michael F. Spear; Arrvindh Shriraman; Luke Dalessandro; Sandhya Dwarkadas; Michael L. Scott (SPAA, 2007)

Flexible Decoupled Transactional Memory Support. - Arrvindh Shriraman; Sandhya Dwarkadas; Michael L. Scott (ISCA, 2008)

Refereeing conflicts in hardware transactional memory. - Arrvindh Shriraman; Sandhya Dwarkadas (ICS, 2009)

Tapping into Parallelism with Transactional Memory. - Arrvindh Shriraman; Sandhya Dwarkadas; Michael L. Scott (login Usenix Mag., 2009)

SPACE: sharing pattern-based directory coherence for multicore scalability. - Hongzhou Zhao; Arrvindh Shriraman; Sandhya Dwarkadas (PACT, 2010)

Sentry: light-weight auxiliary memory access control. - Arrvindh Shriraman; Sandhya Dwarkadas (ISCA, 2010)

Implementation tradeoffs in the design of flexible transactional memory support. - Arrvindh Shriraman; Sandhya Dwarkadas; Michael L. Scott (J. Parallel Distributed Comput., 2010)

SPATL: Honey, I Shrunk the Coherence Directory. - Hongzhou Zhao; Arrvindh Shriraman; Sandhya Dwarkadas; Vijayalakshmi Srinivasan (PACT, 2011)

Analyzing Conflicts in Hardware-Supported Memory Transactions. - Arrvindh Shriraman; Sandhya Dwarkadas (Int. J. Parallel Program., 2011)

Parabix: Boosting the efficiency of text processing on commodity processors. - Dan Lin 003; Nigel Medforth; Kenneth S. Herdy; Arrvindh Shriraman; Robert D. Cameron (HPCA, 2012)

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy. - Snehasish Kumar; Hongzhou Zhao; Arrvindh Shriraman; Eric Matthews; Sandhya Dwarkadas; Lesley Shannon (MICRO, 2012)

Power and energy containers for multicore servers. - Kai Shen; Arrvindh Shriraman; Sandhya Dwarkadas; Xiao Zhang (SIGMETRICS, 2012)

Power containers: an OS facility for fine-grained power and energy management on multicore servers. - Kai Shen; Arrvindh Shriraman; Sandhya Dwarkadas; Xiao Zhang; Zhuan Chen (ASPLOS, 2013)

Verifying safety and liveness for the FlexTM hybrid transactional memory. - Parosh Aziz Abdulla; Sandhya Dwarkadas; Ahmed Rezine; Arrvindh Shriraman; Yunyun Zhu (DATE, 2013)

Protozoa: adaptive granularity cache coherence. - Hongzhou Zhao; Arrvindh Shriraman; Snehasish Kumar; Sandhya Dwarkadas (ISCA, 2013)

An Application-Tailored Approach to Hardware Cache Coherence. - Arrvindh Shriraman; Hongzhou Zhao; Sandhya Dwarkadas (Computer, 2013)

Bitwise data parallelism in regular expression matching. - Robert D. Cameron; Thomas C. Shermer; Arrvindh Shriraman; Kenneth S. Herdy; Dan Lin 003; Benjamin R. Hull; Meng Lin (PACT, 2014)

SQRL: hardware accelerator for collecting software data structures. - Snehasish Kumar; Arrvindh Shriraman; Vijayalakshmi Srinivasan; Dan Lin 003; Jordon Phillips (PACT, 2014)

Cache Coherence for GPU Architectures. - Inderpreet Singh; Arrvindh Shriraman; Wilson W. L. Fung; Mike O'Connor; Tor M. Aamodt (IEEE Micro, 2014)

DASX: Hardware Accelerator for Software Data Structures. - Snehasish Kumar; Naveen Vedula; Arrvindh Shriraman; Vijayalakshmi Srinivasan (ICS, 2015)

Fusion: design tradeoffs in coherent cache hierarchies for accelerators. - Snehasish Kumar; Arrvindh Shriraman; Naveen Vedula (ISCA, 2015)

How to Speed Up CUDA-WSat-PcL by 5x. - Heng Liu; Arrvindh Shriraman; Evgenia Ternovska (CANDAR, 2016)

Peruse and Profit: Estimating the Accelerability of Loops. - Snehasish Kumar; Vijayalakshmi Srinivasan; Amirali Sharifian; Nick Sumner; Arrvindh Shriraman (ICS, 2016)

SPEC-AX and PARSEC-AX: extracting accelerator benchmarks from microprocessor benchmarks. - Snehasish Kumar; William N. Sumner; Arrvindh Shriraman (IISWC, 2016)

Chainsaw: Von-neumann accelerators to leverage fused instruction chains. - Amirali Sharifian; Snehasish Kumar; Apala Guha; Arrvindh Shriraman (MICRO, 2016)

Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs. - Snehasish Kumar; Nick Sumner; Vijayalakshmi Srinivasan; Steve Margerm; Arrvindh Shriraman (HPCA, 2017)

NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators. - Naveen Vedula; Arrvindh Shriraman; Snehasish Kumar; William N. Sumner (HPCA, 2018)

TAPAS: Generating Parallel Accelerators from Parallel Programs. - Steve Margerm; Amirali Sharifian; Apala Guha; Arrvindh Shriraman; Gilles Pokam (MICRO, 2018)

Scalable distributed visual computing for line-rate video streams. - Chen Song; Jiacheng Chen; Ryan Shea; Andy Sun; Arrvindh Shriraman; Jiangchuan Liu (MMSys, 2018)

Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators. - Apala Guha; Naveen Vedula; Arrvindh Shriraman (PACT, 2019)

μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. - Amirali Sharifian; Reza Hojabr; Navid Rahimi; Sihao Liu; Apala Guha; Tony Nowatzki; Arrvindh Shriraman (MICRO, 2019)

Safety-Guaranteed Real-Time Trajectory Planning for Underwater Vehicles in Plane-Progressive Waves. - Seth Siriya; Minh Bui; Arrvindh Shriraman; Mo Chen 001; Ye Pu (CDC, 2020)

Real-Time Formal Verification of Autonomous Systems With An FPGA. - Minh Bui; Michael Lu; Reza Hojabr; Mo Chen; Arrvindh Shriraman (CoRR, 2020)

X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions. - Naveen Vedula; Reza Hojabr; Ahmad Khonsari; Arrvindh Shriraman (PACT, 2021)

SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs. - Reza Hojabr; Ali Sedaghati; Amirali Sharifian; Ahmad Khonsari; Arrvindh Shriraman (HPCA, 2021)

Real-Time Hamilton-Jacobi Reachability Analysis of Autonomous System With An FPGA. - Minh Bui; Michael Lu; Reza Hojabr; Mo Chen 001; Arrvindh Shriraman (IROS, 2021)

mu-grind: A Framework for Dynamically Instrumenting HLS-Generated RTL. - Parmida Vahdatniya; Amirali Sharifian; Reza Hojabr; Arrvindh Shriraman (PACT, 2022)

X-cache: a modular architecture for domain-specific caches. - Ali Sedaghati; Milad Hakimi; Reza Hojabr; Arrvindh Shriraman (ISCA, 2022)

OptimizedDP: An Efficient, User-friendly Library For Optimal Control and Dynamic Programming. - Minh Bui; George Giovanis; Mo Chen; Arrvindh Shriraman (CoRR, 2022)

METAL: Caching Multi-level Indexes in Domain-Specific Architectures. - Anagha Molakalmur Anil Kumar; Aditya Prasanna; Jonathan Balkind; Arrvindh Shriraman (ASPLOS (2), 2024)

TapeFlow: Streaming Gradient Tapes in Automatic Differentiation. - Milad Hakimi; Arrvindh Shriraman (CGO, 2024)

RANGE-BLOCKS: A Synchronization Facility for Domain-Specific Architectures. - Anagha Molakalmur Anil Kumar; Aditya Prasanna; Arrvindh Shriraman (ASPLOS (1), 2025)