Stuck-at-fault testing for quasi-delay-insensitive logic circuits. - Arthit Thongtak; Takashi Nanya (Syst. Comput. Jpn., 1998)

An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic Circuits. - Thanasin Bunnam; Arthit Thongtak (CDES, 2008)

Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits. - Sufian Sudeng; Arthit Thongtak (World Congress on Engineering (Selected Papers), 2008)

Digital scrum board using leap motion. - Patsakorn Rittitum; Wiwat Vatanawood; Arthit Thongtak (ICIS, 2016)

Transformation of the BPMN Design Model into a Colored Petri Net Using the Partitioning Approach. - Chanon Dechsupa; Wiwat Vatanawood; Arthit Thongtak (IEEE Access, 2018)

Hierarchical Verification for the BPMN Design Model Using State Space Analysis. - Chanon Dechsupa; Wiwat Vatanawood; Arthit Thongtak (IEEE Access, 2019)

An Applying Colored Petri Net for Computerized Accounting System and Ledger Accounts Instruction. - Chanon Dechsupa; Wiwat Vatanawood; Worawit Poolsawasdi; Arthit Thongtak (Comput., 2021)

Stepwise Verification for the BPMN With Timed and Stochastic Process Using a Colored Generalized Stochastic Petri Net. - Chanon Dechsupa; Wiwat Vatanawood; Arthit Thongtak (IEEE Access, 2022)

Generating Robot Framework Test Scripts from User Stories and Scenarios for Web Application Testing. - Kritchawat Waitchasarn; Arthit Thongtak; Taratip Suwannasart (ICCCS, 2023)

Toward automated verification of timed business process models using timed-automata networks and temporal properties. - Chanon Dechsupa; Wiwat Vatanawood; Arthit Thongtak (Inf. Sci., 2025)