A Percolation Based VLIW Architecture. - Arthur Abnous; Roni Potasman; Nader Bagherzadeh; Alexandru Nicolau (ICPP (1), 1991)

Special Features of a VLIW Architecture. - Arthur Abnous; Nader Bagherzadeh (IPPS, 1991)

Design and implementation of the 'Tiny RISC' microprocessor. - Arthur Abnous; Christopher Christensen; Jeffrey Gray; John Lenell; Andrew Naylor; Nader Bagherzadeh (Microprocess. Microsystems, 1992)

VIPER: a VLIW integer microprocessor. - Jeffrey Gray; Andrew Naylor; Arthur Abnous; Nader Bagherzadeh (IEEE J. Solid State Circuits, 1993)

Pipelining and Bypassing in a VLIW Processor. - Arthur Abnous; Nader Bagherzadeh (IEEE Trans. Parallel Distributed Syst., 1994)

Evaluation of a Low-Power Reconfigurable DSP Architecture. - Arthur Abnous; Katsunori Seno; Yuji Ichikawa; Marlene Wan; Jan M. Rabaey (IPPS/SPDP Workshops, 1998)

A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing. - Hui Zhang 008; Vandana Prabhu; George Varghese; Marlene Wan; Martin Benes 002; Arthur Abnous; Jan M. Rabaey (IEEE J. Solid State Circuits, 2000)

Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System. - Marlene Wan; Hui Zhang 008; George Varghese; Martin Benes 002; Arthur Abnous; Vandana Prabhu; Jan M. Rabaey (J. VLSI Signal Process., 2001)