A novel hybrid SRAM/DRAM memory architecture for fast packet buffers. - Arthur Mutter (ANCS, 2009)

A generic 10 Gbps assembly edge node and testbed for frame switching networks. - Arthur Mutter; Martin Köhn; Matthias Sund (TRIDENTCOM, 2009)

A novel hybrid memory architecture with parallel DRAM for fast packet buffers. - Arthur Mutter (HPSR, 2010)

A Testbed for Validation and Assessment of Frame Switching Networks. - Arthur Mutter; Sebastian Gunreben; Wolfram Lautenschläger; Martin Köhn (TRIDENTCOM, 2010)

A novel hybrid memory architecture for high-speed packet buffers in network nodes. - Arthur Mutter (2012)