Practical data value speculation for future high-end processors. - Arthur Perais; André Seznec (HPCA, 2014)

EOLE: Paving the way for an effective implementation of value prediction. - Arthur Perais; André Seznec (ISCA, 2014)

BeBoP: A cost effective predictor infrastructure for superscalar value prediction. - Arthur Perais; André Seznec (HPCA, 2015)

Cost-effective speculative scheduling in high performance processors. - Arthur Perais; André Seznec; Pierre Michaud; Andreas Sembrant; Erik Hagersten (ISCA, 2015)

Long term parking (LTP): criticality-aware resource allocation in OOO processors. - Andreas Sembrant; Trevor E. Carlson; Erik Hagersten; David Black-Schaffer; Arthur Perais; André Seznec; Pierre Michaud (MICRO, 2015)

EOLE: Toward a Practical Implementation of Value Prediction. - Arthur Perais; André Seznec (IEEE Micro, 2015)

Increasing the performance of superscalar processors through value prediction. (La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires). - Arthur Perais (2015)

Cost effective physical register sharing. - Arthur Perais; André Seznec (HPCA, 2016)

Register sharing for equality prediction. - Arthur Perais; Fernando A. Endo; André Seznec (MICRO, 2016)

EOLE: Combining Static and Dynamic Scheduling Through Value Prediction to Reduce Complexity and Increase Performance. - Arthur Perais; André Seznec (ACM Trans. Comput. Syst., 2016)

Storage-Free Memory Dependency Prediction. - Arthur Perais; André Seznec (IEEE Comput. Archit. Lett., 2017)

On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE. - Fernando A. Endo; Arthur Perais; André Seznec (ACM Trans. Archit. Code Optim., 2017)

Cost effective speculation with the omnipredictor. - Arthur Perais; André Seznec (PACT, 2018)

SPF: Selective Pipeline Flush. - Vignyan Reddy Kothinti Naresh; Rami Sheikh; Arthur Perais; Harold W. Cain (ICCD, 2018)

Elastic Instruction Fetching. - Arthur Perais; Rami Sheikh; Luke Yen; Michael McIlvaine; Robert D. Clancy (HPCA, 2019)

Take A Way: Exploring the Security Implications of AMD's Cache Way Predictors. - Moritz Lipp; Vedad Hadzic; Michael Schwarz 001; Arthur Perais; Clémentine Maurice; Daniel Gruss (AsiaCCS, 2020)

Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction Potential. - Arthur Perais (MICRO, 2021)

A Case for Speculative Strength Reduction. - Arthur Perais (IEEE Comput. Archit. Lett., 2021)

Free atomics: hardware atomic operations without fences. - Ashkan Asgharzadeh; Juan M. Cebrian; Arthur Perais; Stefanos Kaxiras; Alberto Ros 001 (ISCA, 2022)

Exploring Instruction Fusion Opportunities in General Purpose Processors. - Sawan Singh; Arthur Perais; Alexandra Jimborean; Alberto Ros 001 (MICRO, 2022)

Rebasing Microarchitectural Research with Industry Traces. - Josué Feliu; Arthur Perais; Daniel A. Jiménez; Alberto Ros 001 (IISWC, 2023)

Branch Target Buffer Organizations. - Arthur Perais; Rami Sheikh (MICRO, 2023)

Toward Practical 128-Bit General Purpose Microarchitectures. - Chandana S. Deshpande; Arthur Perais; Frédéric Pétrot (IEEE Comput. Archit. Lett., 2023)

Alternate Path μ-op Cache Prefetching. - Sawan Singh; Arthur Perais; Alexandra Jimborean; Alberto Ros 001 (ISCA, 2024)

Architecting Value Prediction around In-Order Execution. - Pierre Ravenel; Arthur Perais; Benoît Dupont de Dinechin; Frédéric Pétrot (HPCA, 2025)