A 400MHz, 144Kb CMOS ROM Macro for an IBM S/390-Class Microprocessor. - Arthur Tuminaro (ICCD, 1997)

A 8Kb domino read SRAM with hit logic and parity checker. - Antonio Pelella; Arthur Tuminaro; Ryan T. Freese; Yuen H. Chan (ESSCIRC, 2005)

The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane. - Rajiv V. Joshi; Rouwaida Kanj; Anthony Pelella; Arthur Tuminaro; Yuen H. Chan (IEEE Des. Test Comput., 2010)