Asynchronous logic design targeting LUTs. - Igor Lemberski; Artjoms Suponenkovs (MECO, 2018)

Asynchronous logiс one-level LUT design based on partial acknowledgement. - Igor Lemberski; Artjoms Suponenkovs (Microelectron. J., 2018)

LUT-Oriented Asynchronous Logic Design Based on Resubstitution. - Igor Lemberski; Artjoms Suponenkovs; Marina Uhanova (DTIS, 2019)

Resubstitution method for big size Boolean logic design targeting look-up-table implementation. - Igor Lemberski; Artjoms Suponenkovs (Int. J. Circuit Theory Appl., 2021)

Hybrid Approach to Colony-Forming Unit Counting Problem Using Multi-Loss U-Net Reformulation. - Vilen Jumutc; Artjoms Suponenkovs; Andrey Bondarenko; Dmitrijs Bliznuks; Alexey Lihachev (Sensors, 2023)