Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs. - Valery Axelrad; Nicolas B. Cobb; M. O'Brien; Thuy Do; Tom Donnelly; Yuri Granik; Emile Y. Sahouria; Victor Boksha; Artur Balasinski (ISQED, 2000)

Design Strategies for ESD Protection in SOC. - Krzysztof Iniewski; Valery Axelrad; Andrei Shibkov; Artur Balasinski; Marek Syrzycki (IWSOC, 2004)

3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection. - Krzysztof Iniewski; Valery Axelrad; Andrei Shibkov; Artur Balasinski; Sebastian Magierowski; Rafal Dlugosz; Adam Dabrowski (ISCAS (2), 2005)

DfM for SoC, invited. - Artur Balasinski (IWSOC, 2005)

Question: DRC or DfM ? Answer: FMEA and ROI. - Artur Balasinski (ISQED, 2006)