Timing simulation of digital circuits with binary decision diagrams. - Raimund Ubar; Artur Jutman; Zebo Peng (DATE, 2001)

Practical works for on-line teaching design and test of digital circuits. - Artur Jutman; Raimund Ubar; Vladimir Hahanov; O. Skvortsova (ICECS, 2002)

Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods. - Jaan Raik; Artur Jutman; Raimund Ubar (ICECS, 2002)

Asynchronous e-learning resources for hardware design issues. - Artur Jutman; Alexander Sudnitson; Raimund Ubar; Heinz-Dietrich Wuttke (CompSysTech, 2004)

At-speed on-chip diagnosis of board-level interconnect faults. - Artur Jutman (ETS, 2004)

An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. - Artur Jutman; Jaan Raik; Raimund Ubar; V. Vislogubov (DSD, 2005)

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. - Jaan Raik; Raimund Ubar; Sergei Devadze; Artur Jutman (EDCC, 2005)

Off-Line Testing of Delay Faults in NoC Interconnects. - Tomas Bengtsson; Artur Jutman; Shashi Kumar; Raimund Ubar; Zebo Peng (DSD, 2006)

Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. - Sergei Devadze; Jaan Raik; Artur Jutman; Raimund Ubar (LATW, 2006)

DefSim: CMOS Defects on Chip for Research and Education. - Witold A. Pleskacz; Tomasz Borejko; Andrzej Walkanis; Viera Stopjaková; Artur Jutman; Raimund Ubar (LATW, 2006)

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (ETS, 2007)

Learning Digital Test and Diagnostics via Internet. - Raimund Ubar; Artur Jutman; Margus Kruus; Elmet Orasson; Sergei Devadze; Heinz-Dietrich Wuttke (Int. J. Online Eng., 2007)

Parallel fault backtracing for calculation of fault coverage. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (ASP-DAC, 2008)

Calculation of LFSR Seed and Polynomial Pair for BIST Applications. - Artur Jutman; Anton Tsertov; Raimund Ubar (DDECS, 2008)

Reseeding using compaction of pre-generated LFSR sub-sequences. - Artur Jutman; Igor Aleksejev; Jaan Raik; Raimund Ubar (ICECS, 2008)

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. - Tomas Bengtsson; Shashi Kumar; Raimund Ubar; Artur Jutman; Zebo Peng (IET Comput. Digit. Tech., 2008)

DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits. - Witold A. Pleskacz; Viera Stopjaková; Tomasz Borejko; Artur Jutman; Andrzej Walkanis (IEEE Trans. Ind. Electron., 2008)

Structurally synthesized multiple input BDDs for simulation of digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ICECS, 2009)

Fast extended test access via JTAG and FPGAs. - Sergei Devadze; Artur Jutman; Igor Aleksejev; Raimund Ubar (ITC, 2009)

Turning JTAG inside out for fast extended test access. - Sergei Devadze; Artur Jutman; Igor Aleksejev; Raimund Ubar (LATW, 2009)

Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems. - Raimund Ubar; Artur Jutman; Jaan Raik; Sergei Kostin; Heinz-Dietrich Wuttke (MSE, 2009)

Parallel X-fault simulation with critical path tracing technique. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DATE, 2010)

Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DELTA, 2010)

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. - Dmitri Mironov; Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DSD, 2010)

Testing beyond the SoCs in a lego style. - Anton Tsertov; Artur Jutman; Sergei Devadze (EWDTS, 2010)

Fault collapsing with linear complexity in digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ISCAS, 2010)

Structural fault collapsing by superposition of BDDs for test generation in digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ISQED, 2010)

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. - Anton Tsertov; Raimund Ubar; Artur Jutman; Sergei Devadze (Asian Test Symposium, 2011)

SoC and Board Modeling for Processor-Centric Board Testing. - Anton Tsertov; Raimund Ubar; Artur Jutman; Sergei Devadze (DSD, 2011)

Invited paper: System-wide fault management based on IEEE P1687 IJTAG. - Artur Jutman; Sergei Devadze; Igor Aleksejev (ReCoSoC, 2011)

Re-using chip level DFT at board level. - Xinli Gu; Jeff Rearick; Bill Eklow; Martin Keim; Jun Qian; Artur Jutman; Krishnendu Chakrabarty; Erik Larsson (ETS, 2012)

Embedded synthetic instruments for Board-Level testing. - Artur Jutman; Sergei Devadze; Igor Aleksejev; Thomas Wenzel (ETS, 2012)

FPGA-based synthetic instrumentation for board test. - Igor Aleksejev; Artur Jutman; Sergei Devadze; Sergei Odintsov; Thomas Wenzel (ITC, 2012)

On in-system programming of non-volatile memories. - Anton Tsertov; Sergei Devadze; Artur Jutman; Artjom Jasnetski (MIXDES, 2013)

Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. - Artur Jutman; Sergei Devadze; Konstantin Shibin (IEEE Des. Test, 2013)

High Quality System Level Test and Diagnosis. - Artur Jutman; Matteo Sonza Reorda; Hans-Joachim Wunderlich (ATS, 2014)

Design, Verification, and Application of IEEE 1687. - Farrokh Ghani Zadegan; Erik Larsson; Artur Jutman; Sergei Devadze; Rene Krenz-Baath (ATS, 2014)

Asynchronous Fault Detection in IEEE P1687 Instrument Network. - Konstantin Shibin; Sergei Devadze; Artur Jutman (NATW, 2014)

Virtual reconfigurable scan-chains on FPGAs for optimized board test. - Igor Aleksejev; Sergei Devadze; Artur Jutman; Konstantin Shibin (LATS, 2015)

No Fault Found: The root cause. - Erik Larsson; Bill Eklow; Scott Davidsson; Rob Aitken; Artur Jutman; Christophe Lotz (VTS, 2015)

On coverage of timing related faults at board level. - Artur Jutman; Igor Aleksejev; Sergei Devadze (ETS, 2016)

Designing reliable cyber-physical systems overview associated to the special session at FDL'16. - Gadi Aleksandrowicz; Eli Arbel; Roderick Bloem; Timon D. ter Braak; Sergei Devadze; Görschwin Fey; Maksim Jenihhin; Artur Jutman; Hans G. Kerkhoff; Robert Könighofer; Jan Malburg; Shiri Moran; et al. (FDL, 2016)

A suite of IEEE 1687 benchmark networks. - Anton Tsertov; Artur Jutman; Sergei Devadze; Matteo Sonza Reorda; Erik Larsson; Farrokh Ghani Zadegan; Riccardo Cantoro; Mehrdad Montazeri; Rene Krenz-Baath (ITC, 2016)

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs. - Konstantin Shibin; Sergei Devadze; Artur Jutman (LATS, 2016)

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. - Igor Aleksejev; Sergei Devadze; Artur Jutman; Konstantin Shibin (J. Electron. Test., 2016)

BASTION: Board and SoC test instrumentation for ageing and no failure found. - Artur Jutman; Christophe Lotz; Erik Larsson; Matteo Sonza Reorda; Maksim Jenihhin; Jaan Raik; Hans G. Kerkhoff; Rene Krenz-Baath; Piet Engelke (DATE, 2017)

Marginal PCB assembly defect detection on DDR3/4 memory bus. - Sergei Odintsov; Artur Jutman; Sergei Devadze (ITC, 2017)

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure. - Konstantin Shibin; Sergei Devadze; Artur Jutman; Martin Grabmann; Robin Pricken (IEEE Des. Test, 2017)

Run-time reconfigurable instruments for advanced board-level testing. - Igor Aleksejev; Artur Jutman; Sergei Devadze (IEEE Instrum. Meas. Mag., 2017)

A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network. - Sergei Odintsov; Ludovica Bozzoli; Corrado De Sio; Luca Sterpone; Artur Jutman (DDECS, 2019)

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks. - Aleksa Damljanovic; Artur Jutman; Giovanni Squillero; Anton Tsertov (ETS, 2019)

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. - Aleksa Damljanovic; Artur Jutman; Michele Portolan; Ernesto Sánchez 001; Giovanni Squillero; Anton Tsertov (ITC, 2019)

IEEE European Test Symposium (ETS). - Stephan Eggersglüß; Said Hamdioui; Artur Jutman; Maria K. Michael; Jaan Raik; Matteo Sonza Reorda; Mehdi Baradaran Tahoori; Elena-Ioana Vatajelu (ITC, 2019)

HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study. - Natalia Cherezova; Dmitri Mihhailov; Sergei Devadze; Artur Jutman (CoRR, 2022)

On-Chip Sensors Data Collection and Analysis for SoC Health Management. - Konstantin Shibin; Maksim Jenihhin; Artur Jutman; Sergei Devadze; Anton Tsertov (DFT, 2023)

Structural Decision Diagrams in Digital Test - Theory and Applications - Raimund Ubar; Jaan Raik; Maksim Jenihhin; Artur Jutman (Springer, 2024)

IJTAG-compatible Symptom-based SEU Monitors for FPGA DNN Accelerators. - Natalia Cherezova; Maksim Jenihhin; Artur Jutman (DTTIS, 2024)

Keynote: Cost-Efficient Reliability for Edge-AI Chips. - Maksim Jenihhin; Mahdi Taheri; Natalia Cherezova; Mohammad Hasan Ahmadilivani; Hardi Selg; Artur Jutman; Konstantin Shibin; Anton Tsertov; Sergei Devadze; Rama Mounika Kodamanchili; Ahsan Rafiq; Jaan Raik; et al. (LATS, 2024)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference. - Natalia Cherezova; Artur Jutman; Maksim Jenihhin (CoRR, 2025)