An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface. - Navin K. Mishra; Manish Jain; Phuong Le; Sanku Mukherjee; Arul Sendhil; Amir Amirkhany (CICC, 2011)

Self-Calibrating Equalizer for Optimal Jitter Performance Using On-chip Eye Monitoring. - Srinivasaraman Chandrasekaran; Kunal Desai; Arul Sendhil; William Ng (VLSI Design, 2011)

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. - Amir Amirkhany; Jason Wei; Navin K. Mishra; Jie Shen 010; Wendemagegnehu T. Beyene; Catherine Chen 005; T. J. Chin; Deborah Dressler; Charlie Huang; Vijay P. Gadde; Mohammad Hekmat; Kambiz Kaviani; et al. (IEEE J. Solid State Circuits, 2012)

At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems. - Sanku Mukherjee; Srinivasaraman Chandrasekaran; Ganapathy Subramanyan E. K.; Arul Sendhil (VLSI Design, 2013)

A Novel Scheme to Reset through Clock. - Sanku Mukherjee; M. Thrivikraman M.; Anil K. Goyal; Arul Sendhil (VLSI Design, 2013)

A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface. - Vinod Inipodu Murugan; Narayanan Mayandi; Arul Sendhil (VLSID, 2015)